TIVA C UARTIFLS

supreeth anil

Other Parts Discussed in Thread: TM4C123GH6PM

Hello,

I was trying to configure RXIFLSEL and TXIFLSEL for TM4C123GH6PM UART0 as for 1/8 FIFO level (RXIFLSEL - 0x0 and TXIFLSEL - 0x04 respectively)

According to TM4C123GH6PM datasheet

0x0 RX FIFO ≥ ⅛ full

0x4 TX FIFO ≤ ⅛ empty

Will it trigger an interrupt for the following conditions

a) The transmitter buffer goes from 1 to 0 characters

b) The receiver buffer goes from 5 to 6 characters

c) Will it keep on generating interrupts on RX_FIFO empty util we mask it?

Answers to the above mentioned questions will help me in writing a software FIFO using UART0 interrupts

over 8 years ago

0 Amit Ashara over 8 years ago

TI__Guru**** 244400 points

Hello Supreeth

For the interrupts to work the level must be crossed. So if the TX_FIFO is set to 1/8 level then it has to first go to 3 before it can be fired. The same applies for the RX_FIFO as well. When empty it will not re-fire when cleared.

0 supreeth anil over 8 years ago in reply to Amit Ashara

Prodigy 230 points

What will happen if I don't clear the transmit interrupt and the transmit FIFO goes empty? Will it keep on generating an interrupt? If it keeps on generating an interrupt for Transmit FIFO empty condition then I can implement a code for copying software fifo contents into hardware fifo.

0 Amit Ashara over 8 years ago in reply to supreeth anil

TI__Guru**** 244400 points

Hello Supreeth,

If the Interrupt Mask bit is set and the interrupt status is not cleared, the CPU will enter the interrupt handler, exit and then re-enter, causing the loop to take almost all the CPU bandwidth.

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TIVA C UARTIFLS