Can someone be of some assistance with I2C on the Tiva? Here is my problem:
I currently have the I2C running with 2 different I2C modules/buses and several devices. I am trying to incorporate error checking. The situation I am trying to address is a “stuck bus” state. This is where a device is holding the SDA low because a previous bus operation was interrupted and never completed.
To address this I intend to implement the following:
Switch the I2C5 bus signals (PB4 and PB5) to GPIO configuration rather than (input for the SDA, output for the SCL)
Read GPIO PB5, which used to be SDA
If low, loop a number of timer until it goes high
Switch the I2C5 bus signals back to I2C configuration
Go on with normal processing
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Every time the following code gets executed, to return the configuration to I2C, the SCL gets asserted LOW (forever) and has obvious adverse consequences.
GPIOPinConfigure(module->clockPinConfigure); //exactly the same as: MAP_GPIOPinConfigure(GPIO_PB4_I2C5SCL);
GPIOPinTypeI2C(module->clockPort, module->clockPin); // exactly the same as: MAP_GPIOPinTypeI2CSCL(GPIO_PORTB_BASE, GPIO_PIN_4);
GPIOPinConfigure(module->dataPinConfigure); // exactly the same as: MAP_GPIOPinConfigure(GPIO_PB5_I2C5SDA);
GPIOPinTypeI2C(module->dataPort, module->dataPin); // exactly the same as: MAP_GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_5);
Can the pins not be configured like this, except at Power-ON initialization? Do you know what might generating this anomalous behavior?
I suppose another way to achieve this is to not switch the I2C pins, but instead connect another set of GPIO up to the I2C lines and use those GPIO pins to toggle the I2C bus lines when needed but this is an awful waste of other GPIO lines.
Any ideas???
Thanks,
Russ
