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TMS570LC4357: Core jumps to '0x08 - Software interrupt' instead to '0x18 - IRQ'

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hello,

I'm trying to run simple program with gpio interrupt, but processor jumps to invalid address in reset vector.
I put breakpoints from 0x04 to 0x1c. When I push the button -> core immediately jumps to 0x08 instead to 0x18.
Because of breakepoints I can see vim registers and they look fine to me except one:
IrqVecReg contains 0x541 and that is my phantomInterrupt_handler address. Despite the fact that 23th word from address 0xFFF820000 (ISR) contains 0xb69 and that is correct gpioInterrupt_Handler.

Why core jumps to SoftwareInterrupt?

I'm including list of vim registers and screenshoot of paused program and memory view on ISR.


Vim
IrqIVec 0x00000018 Index Offset Vector Register [Memory Mapped]
FiqIVec 0x00000000 Index Offset Vector Register [Memory Mapped]
FIrqPr0 0x00000003 Program Control Register [Memory Mapped]
FIrqPr1 0x00000000 Program Control Register [Memory Mapped]
FIrqPr2 0x00000000 Program Control Register [Memory Mapped]
FIrqPr3 0x00000000 Program Control Register [Memory Mapped]
IntReq0 0x00800000 Pending Interrupt Read Location [Memory Mapped]
IntReq1 0x00000000 Pending Interrupt Read Location [Memory Mapped]
IntReq2 0x00000000 Pending Interrupt Read Location [Memory Mapped]
IntReq3 0x00000000 Pending Interrupt Read Location [Memory Mapped]
ReqMaskSet0 0x00800203 Interrupt Mask Set Register [Memory Mapped]
ReqMaskSet1 0x00000000 Interrupt Mask Set Register [Memory Mapped]
ReqMaskSet2 0x00000000 Interrupt Mask Set Register [Memory Mapped]
ReqMaskSet3 0x00000000 Interrupt Mask Set Register [Memory Mapped]
ReqMaskClr0 0x00800203 Interrupt Mask Clear Register [Memory Mapped]
ReqMaskClr1 0x00000000 Interrupt Mask Clear Register [Memory Mapped]
ReqMaskClr2 0x00000000 Interrupt Mask Clear Register [Memory Mapped]
ReqMaskClr3 0x00000000 Interrupt Mask Clear Register [Memory Mapped]
WakeMaskSet0 0xFFFFFFFF Wake-up Mask Set Register [Memory Mapped]
WakeMaskSet1 0xFFFFFFFF Wake-up Mask Set Register [Memory Mapped]
WakeMaskSet2 0xFFFFFFFF Wake-up Mask Set Register [Memory Mapped]
WakeMaskSet3 0xFFFFFFFF Wake-up Mask Set Register [Memory Mapped]
WakeMaskClr0 0xFFFFFFFF Wake-up Mask Clear Register [Memory Mapped]
WakeMaskClr1 0xFFFFFFFF Wake-up Mask Clear Register [Memory Mapped]
WakeMaskClr2 0xFFFFFFFF Wake-up Mask Clear Register [Memory Mapped]
WakeMaskClr3 0xFFFFFFFF Wake-up Mask Clear Register [Memory Mapped]
IrqVecReg 0x00000541 Irq Interrupt Vector Register [Memory Mapped]
FiqVecReg 0x00000541 Fiq Interrupt Vector Register [Memory Mapped]
CapEvtSrc 0x00000000 Capture Event register [Memory Mapped]
ChanCtrl0 0x00010203 Channel Mapping Register [Memory Mapped]
ChanCtrl1 0x04050607 Channel Mapping Register [Memory Mapped]
ChanCtrl2 0x08090A0B Channel Mapping Register [Memory Mapped]
ChanCtrl3 0x0C0D0E0F Channel Mapping Register [Memory Mapped]
ChanCtrl4 0x10111213 Channel Mapping Register [Memory Mapped]
ChanCtrl5 0x14151617 Channel Mapping Register [Memory Mapped]
ChanCtrl6 0x18191A1B Channel Mapping Register [Memory Mapped]
ChanCtrl7 0x1C1D1E1F Channel Mapping Register [Memory Mapped]
ChanCtrl8 0x20212223 Channel Mapping Register [Memory Mapped]
ChanCtrl9 0x24252627 Channel Mapping Register [Memory Mapped]
ChanCtrl10 0x28292A2B Channel Mapping Register [Memory Mapped]
ChanCtrl11 0x2C2D2E2F Channel Mapping Register [Memory Mapped]
ChanCtrl12 0x30313233 Channel Mapping Register [Memory Mapped]
ChanCtrl13 0x34353637 Channel Mapping Register [Memory Mapped]
ChanCtrl14 0x38393A3B Channel Mapping Register [Memory Mapped]
ChanCtrl15 0x3C3D3E3F Channel Mapping Register [Memory Mapped]
ChanCtrl16 0x40414243 Channel Mapping Register [Memory Mapped]
ChanCtrl17 0x44454647 Channel Mapping Register [Memory Mapped]
ChanCtrl18 0x48494A4B Channel Mapping Register [Memory Mapped]
ChanCtrl19 0x4C4D4E4F Channel Mapping Register [Memory Mapped]
ChanCtrl20 0x50515253 Channel Mapping Register [Memory Mapped]
ChanCtrl21 0x54555657 Channel Mapping Register [Memory Mapped]
ChanCtrl22 0x58595A5B Channel Mapping Register [Memory Mapped]
ChanCtrl23 0x5C5D5E5F Channel Mapping Register [Memory Mapped]
ChanCtrl24 0x60616263 Channel Mapping Register [Memory Mapped]
ChanCtrl25 0x64656667 Channel Mapping Register [Memory Mapped]
ChanCtrl26 0x68696A6B Channel Mapping Register [Memory Mapped]
ChanCtrl27 0x6C6D6E6F Channel Mapping Register [Memory Mapped]
ChanCtrl28 0x70717273 Channel Mapping Register [Memory Mapped]
ChanCtrl29 0x74757677 Channel Mapping Register [Memory Mapped]
ChanCtrl30 0x78797A7B Channel Mapping Register [Memory Mapped]
ChanCtrl31 0x7C7D7E7F Channel Mapping Register [Memory Mapped]


Cp15
CP15_ID_CODE 0x411FC152 MIDR [Core]
CP15_CACHE_TYPE 0x8003C003 CTR [Core]
CP15_TCM_TYPE 0x00010001 TCMTR [Core]
CP15_MPU_TYPE 0x00001000 MPUIR [Core]
CP15_MULTIPROCESSOR_ID 0xC0000000 MPIDR [Core]
CP15_PROCESSOR_FEATURE_0 0x00000131 PFR0 [Core]
CP15_PROCESSOR_FEATURE_1 0x00000001 PFR1 [Core]
CP15_DEBUG_FEATURE_0 0x00010400 DFR0 [Core]
CP15_AUXILIARY_FEATURE_0 0x00000000 ID_AFR0 [Core]
CP15_MEMORY_MODEL_FEATURE_0 0x00210030 ID_MMFR0 [Core]
CP15_MEMORY_MODEL_FEATURE_1 0x00000000 ID_MMFR1 [Core]
CP15_MEMORY_MODEL_FEATURE_2 0x01200000 ID_MMFR2 [Core]
CP15_MEMORY_MODEL_FEATURE_3 0x00000211 ID_MMFR3 [Core]
CP15_INSTRUCTION_SET_ATTRIBUTE_0 0x02101111 ID_ISAR0 [Core]
CP15_INSTRUCTION_SET_ATTRIBUTE_1 0x13112111 ID_ISAR1 [Core]
CP15_INSTRUCTION_SET_ATTRIBUTE_2 0x21232141 ID_ISAR2 [Core]
CP15_INSTRUCTION_SET_ATTRIBUTE_3 0x01112131 ID_ISAR3 [Core]
CP15_INSTRUCTION_SET_ATTRIBUTE_4 0x00010142 ID_ISAR4 [Core]
CP15_INSTRUCTION_SET_ATTRIBUTE_5 0x00000000 ID_ISAR5 [Core]
CP15_CURRENT_CACHE_SIZE_ID 0xF01FE019 CCSIDR [Core]
CP15_CURRENT_CACHE_LEVEL_ID 0x09200003 CLIDR [Core]
CP15_CACHE_SIZE_SELECTION 0x00000000 CSSR [Core]
CP15_SYSTEM_CONTROL 0x8BE50878 SCTLR [Core]
CP15_AUXILIARY_CONTROL 0x00000020 ACTLR [Core]
CP15_COPROCESSOR_ACCESS 0xC0F00000 CPACR [Core]
CP15_DATA_FAULT_STATUS 0x00000000 DFSR [Core]
CP15_INSTRUCTION_FAULT_STATUS 0x00000000 IFSR [Core]
CP15_AUX_DATA_FAULT_STATUS 0x00000000 ADFSR [Core]
CP15_AUX_INSTRUCTION_FAULT_STATUS 0x00000000 AIFSR [Core]
CP15_DATA_FAULT_ADDRESS 0x00000000 DFAR [Core]
CP15_INSTRUCTION_FAULT_ADDRESS 0x00000000 IFAR [Core]
CP15_MPU_REGION_BASE_ADDRESS 0x00000000 Core
CP15_MPU_REGION_SIZE_ENABLE 0x00000000 Core
CP15_MPU_REGION_ACCESS 0x00000000 Core
CP15_MPU_REGION_NUMBER 0x00000000 Core
CP15_TCM_ATCM_REGION 0x00000000 ATCMRR [Core]
CP15_TCM_TCM_SELECTION 0x00000000 TCMSR [Core]
CP15_PERFORMANCE_MONITOR_CONTROL 0x41151800 PMCR [Core]
CP15_COUNT_ENABLE_SET 0x00000000 PMCNTENSET [Core]
CP15_COUNT_ENABLE_CLEAR 0x00000000 PMCNTENCLR [Core]
CP15_OVERFLOW_FLAG_STATUS 0x00000000 PMOVSR [Core]
CP15_SOFTWARE_INCREMENT 0x00000000 PMSWINC [Core]
CP15_COUNTER_SELECTION 0x00000000 PMSELR [Core]
CP15_CYCLE_COUNT 0x00000000 PMCCNTR [Core]
CP15_EVENT_SELECTION 0x00000000 PMXEVTYPER [Core]
CP15_PERFORMANCE_MONITOR_COUNT 0x00000000 PMXEVCNTR [Core]
CP15_USER_ENABLE 0x00000000 PMUSERENR [Core]
CP15_INTERRUPT_ENABLE_SET 0x00000000 PMINTENSET [Core]
CP15_INTERRUPT_ENABLE_CLEAR 0x00000000 PMINTENCLR [Core]
CP15_SLAVE_PORT_CONTROL 0x00000000 AXI Slave Port Control [Core]
CP15_FCSE_PID 0x00000000 FCSEPID [Core]
CP15_CONTEXT_ID 0x00000000 CONTEXTIDR [Core]
CP15_USER_READ_WRITE_THREAD_PROCESS_ID 0x00000000 Core
CP15_USER_READ_ONLY_THREAD_PROCESS_ID 0x00000000 Core
CP15_PRIVILEDGED_ONLY_THREAD_PROCESS_ID 0x00000000 Core
CP15_SECONDARY_AUXILIARY_CONTROL 0x00400000 Core
CP15_NVAL_IRQ_ENABLE_SET 0x00000000 Validation IRQ Enable Set Register [Core]
CP15_NVAL_FIQ_ENABLE_SET 0x00000000 Validation FIQ Enable Set Register [Core]
CP15_NVAL_RESET_ENABLE_SET 0x00000000 Validation Reset Enable Set Register [Core]
CP15_NVAL_DEBUG_REQUEST_ENABLE_SET 0x00000000 Validation Debug Request Enable Set Register [Core]
CP15_NVAL_IRQ_ENABLE_CLEAR 0x00000000 Validation IRQ Enable Clear Register [Core]
CP15_NVAL_FIQ_ENABLE_CLEAR 0x00000000 Validation FIQ Enable Clear Register [Core]
CP15_NVAL_RESET_ENABLE_CLEAR 0x00000000 Validation Reset Enable Clear Register [Core]
CP15_NVAL_DEBUG_REQUEST_ENABLE_CLEAR 0x00000000 Validation Debug Enable Clear Register [Core]
CP15_BUILD_OPTIONS_1 0x00000000 Core
CP15_BUILD_OPTIONS_2 0x403FF9DD Core
CP15_CORRECTABLE_FAULT_LOCATION 0x00000000 Core


PS:
On start I am performing
coreEnableIrqVicOffset:
stmfd sp!, {r0}
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x01000000
mcr p15, #0, r0, c1, c0, #0
ldmfd sp!, {r0}
bx lr

  • Have you tried using HALCoGen to setup the GIO and the VIM?
  • Yes, I have. And I compared generated code with my code. I can't see difference and that is my problem. 

  • When I am using FIQ everything is working fine. 

    And only difference beetween FIQ and IRQ code is:

    vimControl->FIRQPR0 = 0xffffffff;
    vimControl->FIRQPR1 = 0xffffffff;
    vimControl->FIRQPR2 = 0xffffffff;
    vimControl->FIRQPR3 = 0xffffffff;

    that treat all  interrupts as FIQ instead of IRQ

    And Enable Vector Interrupt is set to 1 in CP15_SYSTEM_CONTROL

  • Jacek,

    When you hit the exception at 0x08 (SWI) what does the CPSR register contain?

    Specifically, what are the bits M[4:0] telling you about the processor mode?

    If they say you are in supervisor mode, then it's likely you have a software interrupt instruction (SWI or SVC) somewhere in the code and you accidentally are noticing it just because you put a breakpoint on the vector. This type of instruction may be used behind the scenes normally to perform some task that requires privilege...

    But if you are at the SVC / SWI vector and the CPSR says the mode is IRQ mode, then likely the vector table contents got you there somehow, which could occur if you programmed address 0x00000008 into the VIM RAM in one of the entries and this entry is triggered by an IRQ.
  • I found the solution. 

    Behaviour of CP15 VE is opossite to description and documentation and to code generated by HalcoGen.

  • Thanks Jacek,

    According to the CPU reference manual from ARM, the value in VE means:
    0 = exception vector address for IRQ is 0x00000018 or 0xFFFF0018. See V bit.
    1 = VIC controller provides handler address for IRQ.

    So above, you would be running without the VIM RAM providing the vector to the CPU so you always would
    branch to 0x000018 on an IRQ.

    Are you seeing something different? (where is the error you mentioned exactly ?)

    Also how did this relate to your hitting address 0x08?