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TMS570LC4357: cache ECC mechanisms

Mathieu Patte
Intellectual 440 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hello,

While working with the TMS570LC4357 code, I noticed that the code provided  by Halcogen doesn't enable the cache ECC mechanisms. (it's not included in the cache enable ASM routine). 

Is this intended? I feel that the cache ECC should be enabled by default. 

Mathieu

  • 0
    TI__Guru 68950 points
    Hi Mathieu,

    Interesting observation. I think I see the same, CEC bits of AUXILIARY CONTROL register are 100 after getting to main() in a HalCoGen project and this means "Disable ECC checking" according to the CPU manual Table 8-3 Cache ECC error behavior.

    Let me ask about this to make sure I'm not missing something as well...

    -Anthony