TM4C1294NCPDT: SPI FLASH issue with tm4c1294ncpdt

I'd suggest not using the FSS functionality, just use that pin as a GPIO and do the chip select manually.

Robert

Thanks i configure FSS pin as GPIO pin and do CS manually. Can you confirm if the hardware pin connections in mentioned in original post is correct. We had previous custom board using stellaris and SST25VF040B (spi flash ).

Now we are using tiva and AT25SF041-SSHD-T. The code for creating a file system works in stellaris and i assume it should work in new flash too.

I am able to read the manufacturers and device id (0x9f)

void ReadManufacterID(){
while(SSIDataGetNonBlocking(SSI3_BASE, &pui32DataRx[0])){
}
spi_select();
pui32DataTx[0] = 0x9F;
pui32DataTx[1] = 0;//   dummy
pui32DataTx[2] = 0;//   dummy
pui32DataTx[3] = 0;//   dummy

for(ui32Index = 0; ui32Index < 4; ui32Index++)
{
        SSIDataPut(SSI3_BASE, pui32DataTx[ui32Index]);
}

while(SSIBusy(SSI3_BASE)){
}
for(ui32Index = 0; ui32Index < 4; ui32Index++)
{
SSIDataGet(SSI3_BASE, &pui32DataRx[ui32Index]);
pui32DataRx[ui32Index] &= 0x00FF;
}
spi_deselect();
}

For the filesystem creation i have spi_write function;

uint8_t spi_write(uint8_t out_b) {
        uint8_t M_last_spi_in;
        unsigned long ulTemp;
        SSIDataPut(SSI3_BASE, out_b); // DUMMY
        while (SSIBusy(SSI3_BASE));
        SSIDataGet(SSI3_BASE, &ulTemp);
        M_last_spi_in = ulTemp;
        return M_last_spi_in;
}

The spi_write works for stellaris mcu, any change is needed for tiva.

I guess only change will be in configuring the pins. 

Please correct me if am wrong.

Thank you
Kumar

Hello Kumar,

Where is the CLK pin being configured with GPIOPinConfigure API?

Hi,

Configuring the clock is being done ,posting the entire code for configuration

SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOQ);
SysCtlPeripheralEnable( SYSCTL_PERIPH_GPION);
GPIOPinTypeGPIOOutput(GPIO_PORTQ_BASE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4);
GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_4);
GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_3);
spi_deselect();
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
GPIOPinConfigure(GPIO_PQ0_SSI3CLK);
GPIOPinConfigure(GPIO_PQ3_SSI3XDAT1);
GPIOPinConfigure(GPIO_PQ2_SSI3XDAT0);
GPIOPinWrite(GPIO_PORTQ_BASE, GPIO_PIN_4 , GPIO_PIN_4); // Disable WP
GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_5 , GPIO_PIN_5); // Disable hold
GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
SSIConfigSetExpClk(SSI3_BASE, g_ui32SysClock, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SST25_FLASH_SPI_RATE, 8);
SSIEnable(SSI3_BASE);
Thank you
Kumar

Hello Kumar

The configuration looks correct (it was not matching the code in the first post).

Hi,

Sorry about the error while posting the original code, I took the example you included in this post

e2e.ti.com/.../1361769

I tried doing a and then read and i get this

Starting Program Operations...
Program Completed...
Starting Read Operations...
Read Completed...
Program: 2d Read: 0
Program: cf Read: ff
Program: 46 Read: ff
Program: 29 Read: ff
Program: 4 Read: ff
Program: b4 Read: ff
Program: 78 Read: ff
Program: d8 Read: ff
Program: 68 Read: ff
Program: a7 Read: ff
Program: ff Read: ff
Program: 3f Read: ff
Program: 2b Read: ff
Program: f1 Read: ff
Program: fc Read: ff
Program: d9 Read: ff
Program: 7a Read: ff
Program: 96 Read: ff
Program: 9 Read: ff

I think the write is failing, can you point out why

also i had to comment out the read status register check in write function.
I am manually toggling the CS low and high.

// ui32TempData = SSILibSendReadStatusRegister(ui32Base,0x05);
// while((ui32TempData & 0x02) != 0x02) {
// ui32TempData = SSILibSendReadStatusRegister(ui32Base,0x05);
// }

Thank you
Kumar

Hello Kumar

If you are using the Advanced mode then the configuration is different than what you have done. The FSS (or CS) must be controlled by the SSI controller and not be a GPIO.

Hi,

I made the changes to use the Advanced Mode and i got this
tarting Program Operations...
Program Completed...
Starting Read Operations...
Read Completed...
Program: 2d Read: 0
Program: cf Read: 2d
Program: 46 Read: cf
Program: 29 Read: 46
Program: 4 Read: 29
Program: b4 Read: 4
Program: 78 Read: b4
Program: d8 Read: 78
Program: 68 Read: d8
Program: a7 Read: 68
Program: ff Read: a7
Program: 3f Read: ff
Program: 2b Read: 3f
Program: f1 Read: 2b
Program: fc Read: f1
Program: d9 Read: fc
Program: 7a Read: d9
Program: 96 Read: 7a
Program: 9 Read: 96
Program: 2c Read: 9


I am still trying to find out why it is getting shifted and first address read is 0

Thank you
kumar

Hi,

Thanks i was able to write to flash.
Another question are there any open source file system libraries compatible with tiva?

Thank you
Kumar

Hello Kumar

There is the FatFS that comes with TivaWare which implements fat file system. As far as I know the DK-TM4C129x implements the FAT File System example for the external serial flash in one of the examples on usb.

Hello,

Thanks i will look at it. I am trying to implement the dma based memcpy using this library / code
github.com/.../dma_memcpy

I am getting a weird compilation issue,
arm_atomic.h:29: undefined reference to `__ldrex'
arm_atomic.h:31: undefined reference to `__strex'

Any clue on how to resolve this.I am using arm-non-eabi-4.9.3 version

Thank you
Kumar

Hello Kumar

I have not used any such code example. I am sure there is no instruction like LDREX and STREX for the Cortex M4. Seems to be of Cortex A core origin.

Hi,

Here are two links for more details on LDREX and __ldrex:

LDREX instruction is present in Cortex-M3 and -M4. But there are some problems with the intrinsic implementation in CCS.

Hello Kumar
I have a similar issue, when I try to read any address using ISP I send my read function twice becouse the first data is not the correct value

could you tell me what was your solution?

Regards
Angel B.