TM4C123GH6PM: After 2 CONSECUTIVE GPIO INTERRUPTS MY SSI INTERRUPTS((SSI_RXFF | SSI_RXTO)) DOESNT WORK

Hello Kalyan

Where is the SSI configuration of the interrupt being done?

i do it just before the gpio interrupt configuration

here is the code

#include <stdint.h>
#include <stdbool.h>
#include "outputpins.h"
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_gpio.h"
#include "driverlib/sysctl.h"
#include "driverlib/pin_map.h"
#include "driverlib/rom_map.h"
#include "driverlib/gpio.h"
#include "driverlib/ssi.h"
#include "inc/hw_ints.h"
#include "driverlib/udma.h"
#include "driverlib/flash.h"
#include "utils/flash_pb.h"
#include "driverlib/interrupt.h"

#define MEM_BUFFER_SIZE 1024
#define BUFFERSTOWRITE 10
static uint32_t g_ui32SrcBuf[MEM_BUFFER_SIZE];
static uint32_t g_ui32DstBuf[MEM_BUFFER_SIZE];

uint32_t *p;
uint8_t *P8;
uint32_t FlashStartaddresses=0x400FD000;
uint32_t FlashStopaddresses= 0x400FD032;
uint32_t FlashValue=0;
uint32_t TriggerInt=0;
uint32_t spicmdcnt=0;

uint8_t SetCmd=0;
uint8_t LoopModeEnable=0;

//to get the start index and loopmode enable/disable property
uint8_t ListpModeTrancnt=0;
uint32_t ListpModeStartAddr=0;
uint32_t ListpModeEndAddr=0;
uint32_t ListpModeCnt=0;
uint32_t ListpModeCurrAddr=0;
//*****************************************************************************
//
// The count of SSI0 buffers filled
//
//*****************************************************************************
static uint32_t g_ui32SSIRxCount = 0;

#define NUM_SSI_DATA 8
#define SSI_RXFF_TO 10 // Transmit FIFO is empty
void SSI3_Interrupt(void);
void PortEIntHandler(void);
void slavecmdfunction(void);
void PortBIntHandler();
void Sendtrigger(void);
void SendStoredata(void);
void SysTick_Init(){
//15e6/50e6 = 300ms period
///SysTickDisable();
//SysTickPeriodSet(15000000);
//SysTickEnable();
//NVIC_ST_CURRENT_R = 0;
}

uint32_t pui32DataTx[NUM_SSI_DATA];
uint32_t pui32DataRx[10];
uint32_t pui32DataRx1[32];
uint32_t ui32Index;
uint32_t NumofListModeCMDtostore;
volatile unsigned long g_ulSSI2RXTO = 0;

int main(void)
{
uint8_t Portbdata = 0;
NumofListModeCMDtostore=0;
//Sets the clocking of the device. page 485
//SysCtlClockSet(SYSCTL_SYSDIV_4|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);
SysCtlClockSet(SYSCTL_SYSDIV_2_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);
SysCtlDelay(2500);
uint8_t CLOCKFREQ=SysCtlClockGet();

//
// Enable Peripheral Clocks
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);

//
// Enable pin PA6 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6);

//
// Enable pin PA6 for GPIOOutput
//
GPIOPinTypeGPIOInput(GPIO_PORTE_BASE, GPIO_PIN_0);

//
// Enable pin PA7 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_7);

//
// Enable pin PB7 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_7);

//
// Enable pin PB3 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_3);

//
// Enable pin PB0 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_0);

//
// Enable pin PB2 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_2);

//
// Enable pin PB1 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_1);

//
// Enable pin PB4 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_4);

//
// Enable pin PB6 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_6);

//
// Enable pin PB5 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_5);

//
// Enable pin PC4 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_4);

//
// Enable pin PC5 for GPIOOutput
//
GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_5);

//
// Enable pin PC6 for GPIOInput
//
GPIOPinTypeGPIOInput(GPIO_PORTC_BASE, GPIO_PIN_6);

//
// Enable pin PA2 for SSI0 SSI0CLK
//
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2);

//
// Enable pin PA4 for SSI0 SSI0RX
//
GPIOPinConfigure(GPIO_PA4_SSI0RX);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_4);

//
// Enable pin PA5 for SSI0 SSI0TX
//
GPIOPinConfigure(GPIO_PA5_SSI0TX);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5);

//
// Enable pin PA3 for SSI0 SSI0FSS
//
GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);

//
// Enable pin PD1 for SSI3 SSI3FSS
//
GPIOPinConfigure(GPIO_PD1_SSI3FSS);
GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_1);

//
// Enable pin PD2 for SSI3 SSI3RX
//
GPIOPinConfigure(GPIO_PD2_SSI3RX);
GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_2);

//
// Enable pin PD0 for SSI3 SSI3CLK
//
GPIOPinConfigure(GPIO_PD0_SSI3CLK);
GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0);

//
// Enable pin PD3 for SSI3 SSI3TX
//
GPIOPinConfigure(GPIO_PD3_SSI3TX);
GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_3);

//
// Configure and enable the SSI port for SPI master mode. Use SSI0,
// system clock supply, idle clock level low and active low clock in
// freescale SPI mode, master mode, 1MHz SSI frequency, and 8-bit data.
// For SPI mode, you can set the polarity of the SSI clock when the SSI
// unit is idle. You can also configure what clock edge you want to
// capture data on. Please reference the datasheet for more information on
// the different SPI modes.
//
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 1000000, 16);

SSIConfigSetExpClk(SSI3_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_SLAVE, 1000000, 16);

IntPrioritySet(INT_SSI3,0);
IntPrioritySet(INT_GPIOE,1);

//
// Enable the SSI0 module.
//
SSIEnable(SSI0_BASE);

//
// Enable the SSI0 module.
//
SSIIntClear(SSI3_BASE, (SSI_RXFF |SSI_RXTO));
SSIIntRegister(SSI3_BASE, SSI3_Interrupt);
SSIIntEnable(SSI3_BASE, (SSI_RXFF | SSI_RXTO));
SSIIntClear(SSI3_BASE, (SSI_RXFF | SSI_RXTO));
SSIEnable(SSI3_BASE);
SysCtlDelay(2500);

GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_PIN_0, GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
//configure gpio intruppet
GPIOIntTypeSet(GPIO_PORTE_BASE,GPIO_PIN_0,GPIO_BOTH_EDGES );
GPIOIntRegister(GPIO_PORTE_BASE,PortEIntHandler);
uint32_t status=0;
status = GPIOIntStatus(GPIO_PORTE_BASE,true);

GPIOIntClear(GPIO_PORTE_BASE,GPIO_PIN_0);
GPIOIntEnable(GPIO_PORTE_BASE, GPIO_INT_PIN_0);

// FlashProtectSet(FlashStartaddresses,FlashReadWrite);
//p=FlashStartaddresses;
//
// Read any residual data from the SSI port. This makes sure the receive
// FIFOs are empty, so we don't read any unwanted junk. This is done here
// because the SPI SSI mode is full-duplex, which allows you to send and
// receive at the same time. The SSIDataGetNonBlocking function returns
// "true" when data was returned, and "false" when no data was returned.
// The "non-blocking" function checks if there is any data in the receive
// FIFO and does not "hang" if there isn't.

SendStoredata();

SSIDataPut(SSI0_BASE, 0X4C4D);//listmode start

SSIDataPut(SSI0_BASE,0X0C05);//

SSIDataPut(SSI0_BASE, 0x1401);

while(1)
{

while(SSIBusy(SSI0_BASE))
{
}

Sendtrigger();
SysCtlDelay(250);
Sendtrigger();

SysCtlDelay(250);
//GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6,0);
//Sendtrigger();
//SysCtlDelay(250);
//Sendtrigger();
//GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6,0);
// SSIEnable(SSI3_BASE);
// SSIIntEnable(SSI3_BASE, (SSI_RXFF | SSI_RXTO));
// SSIIntClear(SSI3_BASE, (SSI_RXFF | SSI_RXTO));

SSIDataPut(SSI0_BASE, 0X534D);
SSIDataPut(SSI0_BASE, 0X534D);
SSIDataPut(SSI0_BASE, 0X534D);
SSIDataPut(SSI0_BASE, 0X534D);
SSIDataPut(SSI0_BASE, 0X534D);
//status=SSIIntStatus(SSI3_BASE,0);
while(SSIBusy(SSI0_BASE))
{
}
// SysCtlDelay(250);
// GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0,0);
// GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0,1);

SSIDataPut(SSI0_BASE, 0X4F46);
SSIDataPut(SSI0_BASE, 0x01);
SSIDataPut(SSI0_BASE,0x02);
SSIDataPut(SSI0_BASE, 0X4446);

//uint32_t returnadd= FlashProgram(pui32DataRx1,FlashStartaddresses, sizeof(pui32DataRx1));
SysCtlDelay(25000);

//SSIDataPut(SSI0_BASE, 0X4C4D);
//FlashValue=*p;
SysCtlDelay(25000);

}

}

void SendStoredata(void)
{
SSIDataPut(SSI0_BASE, 0x5354);//start storing

SSIDataPut(SSI0_BASE, 0x01);
SSIDataPut(SSI0_BASE, 0x02);
SSIDataPut(SSI0_BASE, 0x03);
SSIDataPut(SSI0_BASE, 0x0A);
SSIDataPut(SSI0_BASE, 0x0B);
SSIDataPut(SSI0_BASE, 0x0C);

SSIDataPut(SSI0_BASE, 0x0D);
SSIDataPut(SSI0_BASE, 0x0E);
SSIDataPut(SSI0_BASE, 0x0F);
SSIDataPut(SSI0_BASE, 0x12);
SSIDataPut(SSI0_BASE, 0x23);
SSIDataPut(SSI0_BASE, 0x18);

SSIDataPut(SSI0_BASE, 0x31);
SSIDataPut(SSI0_BASE, 0x32);
SSIDataPut(SSI0_BASE, 0x33);
SSIDataPut(SSI0_BASE, 0x3A);
SSIDataPut(SSI0_BASE, 0x3B);
SSIDataPut(SSI0_BASE, 0x3C);

SSIDataPut(SSI0_BASE, 0x3D);
SSIDataPut(SSI0_BASE, 0x3E);
SSIDataPut(SSI0_BASE, 0x3F);
SSIDataPut(SSI0_BASE, 0x32);
SSIDataPut(SSI0_BASE, 0x33);
SSIDataPut(SSI0_BASE, 0x38);

SSIDataPut(SSI0_BASE, 0x4D);
SSIDataPut(SSI0_BASE, 0x4E);
SSIDataPut(SSI0_BASE, 0x4F);
SSIDataPut(SSI0_BASE, 0x42);
SSIDataPut(SSI0_BASE, 0x43);
SSIDataPut(SSI0_BASE, 0x48);

SSIDataPut(SSI0_BASE, 0X5350);//stopstoring
}
void Sendtrigger(void)
{
GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6,0);
GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6,64);
}
void SSI3_Interrupt(void)
{

ui32Status=SSIIntStatus(SSI3_BASE,0);

//dosomething

SSIIntClear(SSI3_BASE, (SSI_RXFF |SSI_RXTO));

}

Hello Kalyan

What about IntEnable(INT_SSI3)?

Doing SSIIntEnable(SSI3_BASE, (SSI_RXFF | SSI_RXTO)); should enable the interrupt.?
I tried doing this IntEnable(INT_SSI3) and still it did not work.
The ssi interrupt works if i dont have the gpio interrupts or trigger the gpio interrupt only once.

You need (both) of those interrupt functions. Review of Examples/Peripherals/SSI should provide known good code samples...

Hello Kalyan,

There is no reason and logic why the GPIO interrupt should interfere with the SSI interrupt. The only reasons I see why the SSI may not interrupt is (a) there is nothing in the SSI RXFIFO and (b) The SSI address space is open in the debugger causing data to be read out.

ok i debug future and found that for some reason after writing gpio port b( allpins) for 20 times or more( write to port b after  the gpio interrupt occurs) my ssi interrupt is getting disabled.If i enable the ssi interrupt each time i write to a gpio port my ssi works fine.Which still doesnt make sense.

Is there a reason/condition where ssi interrupt get disabled if  the ssi bus is idle for some time ?

Hello Kalyan

I can't think of any logical reason why writing GPIO port B for 20 times or more would affect the SSI interrupt. Now where is the SSI interrupt getting disabled. In the peripheral's SSIIM register or the NVIC?