Other Parts Discussed in Thread: TMS570LS2124
Hi,
My situation is as follows:
There is a Hercules processor (currently TMS570LC4357 but we may also use the TMS570LS2124) that is communicating with an FPGA using a MibSPI bus. The transactions to the FPGA consist of a 16 bit header word that identifies a particular channel on the FPGA, the memory address of that channel and the action to take (read / write, reset, etc), along with data read or write to / from the FPGA.
As an example, an FPGA channel may be reading pulse widths from external devices and updating it's internal memory with the most recent info about that pulse width. The CPU will read data from the FPGA regarding that pulse width. However, it will be very easy to run into collisions where the FPGA is updating the pulse width register while the CPU wants to read it. In that case, the CPU must delay the SPI transaction, which can be done using the SPIENAn pin, based on my reading.
However, it won't be possible to delay the CPU until the FPGA has received the header word, which will be in the middle of the transaction. Before the header word is received, the FPGA will not know which channel is being accessed and so it won't be able to assess whether or not it needs to hold the CPU. If there is no need to hold, it can provide the data right away, but if the memory is in use it will need to wait until the next FPGA clock to access the memory, which means it won't get to the SPI bus in time to send out.
So, my question boils down to 'Can the SPI Enable pin be used to hold a transaction midway through the transaction?'
