TM4C1294KCPDT: How to achieve maximum sample rate by ADC Differential input

Hello Janet

How has the ADC been configured. Could you please post the code for the same?

Hi Amit:

ADC configure as below .thanks

/*
* main.c
*/
#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/tm4c1294kcpdt.h"
#include "driverlib/pin_map.h"
#include "driverlib/sysctl.h"
#include "driverlib/debug.h"
#include "driverlib/gpio.h"
#include "driverlib/adc.h"
#include "driverlib/rom.h"
#include "driverlib/timer.h"
#include "driverlib/interrupt.h"

// ****** Constants ******
const int sampleFreq = 8000; // Sample Frequency

// ****** Variables ******
uint32_t ADC0Value[1024];
uint16_t samplePeriod;
uint32_t ui32SysClock;
uint32_t uState;
uint32_t diff;

// Interrupts
void Timer0IntHandler(void){
ROM_TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
uint32_t ugpio;
ugpio = GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_4);
if(ugpio == GPIO_PIN_4)
{
GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_4, 0);
}
else
{
GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_4, GPIO_PIN_4);
}

}

void ADC0SS3IntHandler(void){

ROM_ADCSequenceDataGet(ADC0_BASE,3,ADC0Value); // Get Data from ADC and store it in ADC0Value
ADCIntClear(ADC0_BASE, 3);
diff = ADC0Value[0];

if(diff >= 200)
{
GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_PIN_5);
}
else if (diff <= 100)
{
GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_5, 0);
}
}

// Definitions
void systemSetup(void){
// *** Clock

#if defined(TARGET_IS_TM4C129_RA0) || \
defined(TARGET_IS_TM4C129_RA1) || \
defined(TARGET_IS_TM4C129_RA2)

ui32SysClock = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_480), 120000000);
#else
SysCtlClockSet(SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_25MHZ);
#endif

// *** Peripheral Enable
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
// ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);

ROM_SysCtlDelay(100);
HWREG(SYSCTL_BASE + 0x538) = 0x03;
ROM_SysCtlDelay(50);
HWREG(SYSCTL_BASE + 0x538) = 0x00;
ROM_SysCtlDelay(100);

// *** ADC0
ROM_ADCReferenceSet(ADC0_BASE,ADC_REF_INT);
ROM_ADCSequenceConfigure(ADC0_BASE,3,ADC_TRIGGER_TIMER,0);
// ROM_ADCSequenceStepConfigure(ADC0_BASE, 2, 0, `15);
// ROM_ADCSequenceStepConfigure(ADC0_BASE, 2, 1, ADC_CTL_CH14 | ADC_CTL_IE | ADC_CTL_END);
// ROM_ADCSequenceStepConfigure(ADC0_BASE, 2, 0, ADC_CTL_CH7 | ADC_CTL_D | ADC_CTL_IE | ADC_CTL_END);
ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0, ADC_CTL_CH7|ADC_CTL_D|ADC_CTL_IE|ADC_CTL_END);//ADC_CTL_CH7
ROM_ADCSequenceEnable(ADC0_BASE, 3);

// *** GPIO
// PD0, PD1 as ADC
ROM_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1);

// PD2, PD3 as Input
ROM_GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_2 | GPIO_PIN_3);
GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_PIN_2 | GPIO_PIN_3,
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
// PA4, PA5 as Output
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_4 | GPIO_PIN_5);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_4 | GPIO_PIN_5,
GPIO_STRENGTH_12MA, GPIO_PIN_TYPE_STD);

// *** Timer
ROM_TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC);
ROM_TimerLoadSet(TIMER0_BASE, TIMER_A, ui32SysClock / 200000);
TimerControlTrigger(TIMER0_BASE, TIMER_A, true);

// *** Interrupts
ROM_IntEnable(INT_TIMER0A);
ROM_TimerIntEnable(TIMER0_BASE,TIMER_TIMA_TIMEOUT);
ROM_IntEnable(INT_ADC0SS3);
ROM_ADCIntEnable(ADC0_BASE,3);

ROM_IntMasterEnable();
ROM_TimerEnable(TIMER0_BASE,TIMER_A);
}

int main(void) {
systemSetup();

while(1){
}

return 0;
}

test result:

1. PD0 PD1 Connection to GND both.

 

         2.PD0 PD1 Connection to 3V3 both.

 

Hello Jimmy,

So the issue is a large variation in the differential value when both pins are connected to either GND or to 3.3V on the LaunchPad? This has got nothing to do with 2 MSPS. Is that correct?

What I see in the code is that the Channel 7 is configured for Differential mode but PD0 and PD1 are ADC pins corresponding to Channel 15 and 14. You must use ADC_CTL_CH14 instead of ADC_CTL_CH7 in the configuration if PD0 and PD1 must be used.