Lenovo hardware EA want to know why I2C clock duty cycle is about low 60%, high 40% in TM4C123B.
Seems it is fixed value in MCU specification under low speed mode.
Our datasheet described as below:
"SCL_LP is the low phase of SCL (fixed at 6)"
"SCL_HP is the high phase of SCL (fixed at 4)"
Can you help to share some information for this signal?
Because they expected it should be low 50%, high 50%. Thanks!
