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RM57L843: Instruction execution from RAM or FLASH

Praveen P
Prodigy 160 points
Part Number: RM57L843

Hi,

I am working on RM57L843 device from last one month.I have one basic doubt..

As per my knowledge and the reference manual of the device, after power on the RM57L843 device start executing from 0x00000 flash location where reset vector is located.

Is it possible to run the application say bootloader application from RAM location?

In debug mode (putting break point single step execution) the application is loaded into flash or RAM?

Thanks & regards,

Praveen

  • 0
    TI__Guru 68920 points
    Hi Praveen,

    It is not possible to relocate the vector table to an address other than 0x00000000 which is always mapped to flash.
    (this device does not have an MMU or virtual memory).

    The CPU supports a HIVECS mode where it can relocate the vector table to 0xFFFF0000 but you cannot make use of that mode
    with Hercules because it maps to some address range used for peripherals not memory.

    It is possible to map most of your IRQ ISRs to RAM directly, bypassing flash, because in the vectored IRQ mode the CPU bypasses address 0x00000018 and jumps directly to an address provided by the VIM. But you still need the vector table at address 0x00 for the other exceptions, the CPU only accepts vectored IRQs .

    It is always possible to load some program into RAM and execute under debug control and in fact the flash programming algorithms that CCS uses do this in the background without you knowing [they do first save then later restore the RAM contents so the process is invisible to you]. But that's not useful unless there is a debugger attached.

    There are bootloader examples for Hercules in the application notes section of the product folder. The bootloaders do some sort of secondary branch from the exception vector at address 0x00000000 to another vector table you can create in the sectors above the bootloader. This is tricky and we get a lot of people having trouble w. this method, but it can work.

    On the RM57L please note that the device is cache based, and that the I$ and D$ are separate. When you copy code from flash to RAM it is done as a 'data' transfer so it is important to: a) make sure you either flush the D$ or use a write through mode, so that the program you copy is actually written to L2SRAM not just stored in a dirty cache line. b) flush the I$ so that it doesn't have a stale copy of data at that address. To Recap: there isn't any sort of HW that keeps the L1I$ and L1D$ coherent for you so when operating on 'code' as 'data' (like doing a memcpy()) you have to handle this coherency issue in SW...

    -Anthony