TMS570LC4357: Implementation rules for TMS570LC4357

Maxime,

We do not have any specific implementation guidelines for TMS570LC4357.

A good practice would be to put a decoupling capacitor for each power/ground pair and to use power planes.

You can look at the HDK or LaunchPad for examples.

-Anthony

Thanks for your answer, 

Please find below additional question from customer, 

We had a look on the HDK and Launchpad boards, which all have the decoupling capacitors bellow the BGA.

However, this is not clear for us if this placement of the decoupling capacitor just below the BGA ball is mandatory of if we can place this capacitors next to the BGA instead. This placement (Case 2 in the figure) has manufacturing advantages, but could generate issues on the power lines, since the path between the capacitor and the power ball of the TMS is long (~2 cm).

The impact on our board layout and manufacturing process is important, we would like to know if there is some field return from TI that would forbid, or strongly disadvise the second solution.

Thank you in advance,

Hello team,

Could you please advise ? Thanks, Maxime

Maxime,

We don't have any published guidelines for PCB layout on this product and I don't want to make any sort of guess as to which of your scenarios is better. You should actually be able to calculate this by knowing more specifics, like the via inductance, the PCB stackup, and capacitor size / routing to the via.

The only concern we really have would be if the voltage spikes outside the recommended operating condition range during operation. You need to verify on your hardware that it does not. The amount that the power rail moves during operation is going to be a function of the impedance of your power distribution network which is what you are asking about ... and the switching currents of the device which will largely depend on the software you are running.

The only suggestions I have are to get a good handbook and employ best practices, plus do some calculations to estimate the impedance of your network for your two scenarios. And take into account that being on the top layer outside the perimeter you may wind up being closer to the VDD/GND planes than on the bottom side [Depending on your stackup] and you may have more flexibility in vias to connect to that plane.

You can also design your PCB with several footprints for capacitors under the device and the rest outside, and then check the actual performance on your prototypes.

Thanks and Best Regards,
Anthony

Hi Maxime,

I agree with Anthony's suggestions. Many calculations is required to determine how many decoupling capacitors are needed and where to put those caps to ensure the power supply under all operating conditions is lower than the specified limits (for example, 5% tolerance rating of 3.3V IO power supply).  

Droop = L*(Max(dI/dt) = L*(1.52*delta(V)*C/(Tr)^2)

For a 2cm trace, the inductance is estimated as: L=2cm*600nH/m=12nH

Tr(risetime) = 4ns (8mA Low EMI pins) for C(load)=50pF, delta(V) = 80%*3.3=2.64V

Droop = 12*[1.52*2.64/16*50] =0.15V  --> this is the case for without the decoupling caps, or the decoupling caps are placed >2cm far away from the pins.  

The number of I/O decoupling caps (for example 0.01uF):  C=I(io total)*dt/dVio; dt is the fastest risetime, and dVio is the maximum ripple allowed for the IO voltage (for example 50mv ripple)

The total IO current is not equal to the IO current consumption of the MCU itself. The majority of the IO current depends on the external load, for example resistive, capacitive or transmission line.

In general, the idea way to decouple the supply noise is having 1 capacitor between each of the power pins and ground. Normally this is very hard because the MCU package area is very small. So, the formula mentioned above can be used to calculate the minimum number of decoupling capacitors should be used. So here are my consideraions for the decoupling capacitors:

1. add as many decoupling capacitors as space allows

2. place the capacitors as close to the power pins as you can (you can place some underneath the MCU, and some at the edge of the MCU). 

3. add 2 or more  bulk capacitors (Vcc, and Vio) as a low frequency noise filter and a charge storage device for the small decoupling capacitors.

4. Since capacitor has ESL and ESR which reduce filtering effectiveness, so select the smallest surface mount capacitors.

Regards,

QJ

Hello,

Appreciate for your detail feedback, 

I will let my customer reply directly to the post,

Thanks,Maxime

Hi Maxime,

Droop = 12*[1.52*2.64/16*50] =0.15V  --> this is the case for without the decoupling caps, or the decoupling caps are placed >2cm far away from the pins.  

This is only for the case without the decoupling capacitors.

Regards,

QJ