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TMS570LS3137: Please tell me the changing conditions of InitDbg

Part Number: TMS570LS3137

I use TMS570LS3137.

Please tell me the conditions that change InitDbg of CAN Control Register from 1 to 0.
InitDbg stays at 1 even though CAN transmission can be confirmed on CANoe.

  • Hi,
    The InitDbg is set when the CAN enters debug state. It is cleared when it exits the debug state. When the CPU is halted (i.e. when you single step in the deubgger when the a breakpt is taken) it sends out a dbg_ack signal to the rest of the system. The signal is read by the CAN module. Whether or not the CAN enters debug state when the dbg_ack is set will depend on another bit called IDS (Interruption Debug Support Enable). This bit is in the DCAN CTL register. When IDS is set and dbg_ack is also asserted, the DCAN module will immediately enters debug state. When dbg_ack is de-asserted from the CPU, the InitDbg will clear to 0.