TM4C1294NCPDT: Parallel bus (EPI interface) between TM4C1294NCPDT and FPGA

Sergey,
I don't exactly know the EPI interface, but I can give one suggestion for a "fast parallel data transfer":
If you are talking external->TM4C, you can connect the lines into GPIO's, and configure a DMA transfer from the GPIO registers addresses into a desired memory location.
This DMA could be triggered by a level change on the Clock signal, provided that the communication clock is controlled by your external device.
If the transfer is to send data, the same idea can be applied - copy memory to GPIO registers and then clock the output transfer.
However, "fast speed" need to be better defined. What sort of clock and data rate do you actually need? Will there be processing power available on the MCU to do something with that data?
Regards,
Bruno

Hello Sergey

In General purpose mode of EPI you can get 16 Data pins and 12 address pins along with Clock, Read and Write. There is no iRDY provision.

In Host bus mode you can get all of the above, however the Address and Data would be multiplexed.

Sergey,

Is there a better diagram of the EPI bus operation than the one on page 852, Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0? One that shows the clock,read, and data timing relationship.

Ron

Hello Ronald

The Figure shows toggles at every EPI clock. I agree it is not very clear.

Hello Ronald

ronald grush said:

One or two more clock

Not very clear what you meant here?

"One or two more clock, read, data cycles would be very helpful."

Like in Figure 11-22, but showing the data signal on reads or in Figure 27-25 showing multiple read cycles.

I have everything working now, thanks for the help,

Ron