HalCoGen and SCI CLOCK settings

Hello Olaf,

Sorry for the confusion as the interchangeable use of different names for the same thing can be very confusing confusing and we seem to do this too often with the peripheral clock.

In this case the VBUSPCLK is used to designate the peripheral clock in the SCI chapter. It is used instead of VCLK1 since SCI can be placed in any peripheral clock clock domain. Dependent on the architecture of the device, it could be VCLK1,  VCLK2, VCLK3, etc. To make a determination of which domain you would need to identify which clock domain the peripheral resides in. This can be done using the clock domain mapping figure in section 6-6 within the device datasheet SPNS238D.pdf. Another twist here is that there is no VCLK1 noted in the diagram but VCLK = VCLK1 in this context. Again, sorry for that. I've entered a documentation ticket to note the inconsistency in the nomenclature.

Generally speaking, SCI modules usually reside in VCLK1 domain. Given you have adjusted HCLK to 150MHz and changed the divider of VCLK2 to 3 to achieve 50MHz for VCLK2; did you do the same to the VCLK1 divider to also achieve the 50MHz clock on VCLK1? HCLK is the source for both VCLK1 and VCLK2 so both dividers would need to be adjusted if you change HCLK.

Hi Chuck

Thanks for your answer. I don’t quarrel with the names of the clocks and I would be glad to find an own error, but when we agree that VCLK, VCLK1 and VBUSPCLK are the same in the context the result seems not to be deterministic?

With unchanged SCI4 settings

 

This one is working with the expected baud rate (8,68 µs/Bit ~ 115200 Baud)

but this one doesn’t work (5,8 µs/Bit ~ 172800 Baud ?)

But in chapter 2.4.2 Clock Domains, Table 2-10. Clock Domains, in SPNU563.pdf I found:

• HCLK:VCLK2:VCLK must be integer ratios of each other

In this case
VCLK2 : VCLK  =  75 : 50 = 1.5
would be illegal configuration  and should be blocked by HALCOGEN?

Best Regards

Olaf

Olaf,

Good catch on this. I wasn't aware of the restriction. I know there were some significant changes to the clock structure in the LC4357 so perhaps this is a resulting limitation within this device. I will forward your suggestion to limit the ratios within Halcogen as well, but I fear that this may be considered beyond the scope of HalCoGen's capability.

For now, I am glad that you found the issue. Are you able to find a work around for the limitation to make your code work properly?

Hi Chuck,

If there is a known restriction, it is no problem to work around. I am newbie with this device and each time I touched Halcogen, first result was:CCS Software does not compile any longer or target does not run as expected. It would be very helpful if Halcogen rejects illegal settings. At least the restriction should be part of the notes which are already part of the tool:

VCLK2 >= VCLK(1) AND integer ratio for HCLK : VCLK2 : VCLK(1)     (add at least this line to the Notes)

If VCLK can silently change from 50 to 75 MHz without having this change visible in the configuration tool it is very hard to understand the behavior of the generated code.

Thanks for forwarding

Best Regards

Olaf