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About diagnostic method of "RAM6".

Sazabi
Intellectual 270 points
Other Parts Discussed in Thread: TMS570LS3137

Hi,

I currently use TMS570LS3137.
(Reference document = "Safety Manual for TMS 570LS31x and TMS570L21x Hercules ARM-Based Safety Critical Microcontrollers User's Guide")

Please tell me about "RAM6" items.

"Safety Manual" contains the following.
>> This scheme provides an inherent safety mechanism for address decode failures in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an ECC fault.

(1) If this fault is detected by the CPU as an ECC fault, will the detected error be output to "ESM channel"?

(2-1) If the detected error is output to the ESM, can you detect an error of "RAM 6" by checking the following channel of ESM (all channels or specific channel)?
- RAM even bank (B0TCM) - correctable error. (Group 1, Channel 26)
- RAM odd bank (B1TCM) - correctable error. (Group 1, Channel 28)
- RAM even bank (B0TCM) - uncorrectable error. Group 2, Channel 6)
- RAM odd bank (B1TCM) - uncorrectable error. (Group 2, Channel 8)
- RAM even bank (B0TCM) - uncorrectable error. Group 3, Channel 3)
- RAM odd bank (B1TCM) - uncorrectable error. (Group 3, Channel 5

(2-2) If the detected error is not output to the ESM, is there a way to implement the self test of "RAM 6"?

  • 0
    TI__Guru 59540 points

    Sazabi said:
    (1) If this fault is detected by the CPU as an ECC fault, will the detected error be output to "ESM channel"?

    Yes.

    Sazabi said:
    (2-1) If the detected error is output to the ESM, can you detect an error of "RAM 6" by checking the following channel of ESM (all channels or specific channel)?
    - RAM even bank (B0TCM) - correctable error. (Group 1, Channel 26)
    - RAM odd bank (B1TCM) - correctable error. (Group 1, Channel 28)
    - RAM even bank (B0TCM) - uncorrectable error. Group 2, Channel 6)
    - RAM odd bank (B1TCM) - uncorrectable error. (Group 2, Channel 8)
    - RAM even bank (B0TCM) - uncorrectable error. Group 3, Channel 3)
    - RAM odd bank (B1TCM) - uncorrectable error. (Group 3, Channel 5

    You would troubleshoot the error in the same way that you would any other ECC error condition. The premise behind this mechanism is that physically locating the data and ECC data in different banks would mean that there would have to be a double fault in addressing the data and addressing the ECC data. Essentially, this relies on the the fact that the probability of addressing to both banks being faulty at the same time AND still resulting in the proper pairing of data and ECC data is extremely remote. This type of error almost always result in an uncorrectable error. Specifically, ESM Group 3, Channels 3 and 5 will be set. The Group 2 ESM flags would not apply.

  • 0 in reply to Chuck Davenport
    Intellectual 270 points
    Hello Chuck,

    Thank you for answering.
    I understood the mechanism of error output of "RAM 6".

    Chuck wrote,
    >> ESM Group 3, Channels 3 and 5 will be set. The Group 2 ESM flags would not apply.

    In this case, I think that the error of "RAM 6" will be output using the same channel as the error of "RAM 1", but is there a way to distinguish between "RAM 6" and "RAM 1" errors?

    Best Regards,

    Sazabi
  • 0 in reply to Sazabi
    TI__Guru 59540 points
    Hello Sazabi,

    Some additional diagnostics might be possible, but, even a re-read of the address causing the uncorrectable error (address is stored in the uncorrectable error register) might only demonstrate that the fault was a transient or permanent faulure. Like several others related to ECC, this mechanism is identified as a fault avoidance mechanism for this very reason of reporting a problem but lacking the ability to identify the root cause in a deterministic way. Fault avoidance measures are not considered in the calculation of DC so this shouldn't impact overall safety metrics.