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PMU counter

Other Parts Discussed in Thread: HALCOGEN

I'm reading "Chapter 6" of "Cortex™-R4 and Cortex-R4F (Revision: r1p3)".

I have a question about "Performance Monitoring Unit (PMU)".

Each "6.3.8 c9, Event Selection Register" selects the events I want a PMC Register to count.

I think there should be three counters(EVTSEL0,EVTSEL1,EVTSEL2), Although I can find only one(maybe EVTSEL0) register to set.

Please refer the image below.

Similarly, "6.3.9 c9, Performance Monitor Count Registers" I can find only one register(maybe PMC0).

I want to know how to selects the three counters counts event by "Event Selection Register".

And I want to know how do count three events by "Performance Monitor Count Registers".

  • Hello Arriy,

    The event selection and other registers within the PMU are banked registers. To access them you must first select the the counter you are using via the PMNXSEL register (see section 6.3.6 in the Cortex-R4 and R4F r1p3 TRM you referenced.

    i.e., if you write b00000 in the PMNXSEL register, you will be working with EVTSEL0 and PMC0. If you write b00001 to the PMNXSEL register, it will be EVTSEL1 and PMC1, and so on.

    As a simple example, this is the init code generated by HalCoGen. Note the indexing of r0 to index to the different counter and selection registers.

    ;-------------------------------------------------------------------------------
    ; Initialize Pmu
    ; Note: It will reset all counters
    
        .def     _pmuInit_
        .asmfunc
    
    _pmuInit_
    
            stmfd sp!, {r0}
            ; set control register
            mrc   p15, #0, r0, c9, c12, #0 
            orr   r0,  r0, #(1 << 4) + 6 + 1
            mcr   p15, #0, r0, c9, c12, #0
            ; clear flags
    		mov   r0,  #0
    		sub   r0,  r0,  #1
    		mcr   p15, #0, r0, c9, c12, #3 
            ; select counter 0 event
            mcr   p15, #0, r0, c9, c12, #5 ; select counter
            mov   r0,  #0x11
            mcr   p15, #0, r0, c9, c13, #1 ; select event
            ; select counter 1 event
    		mov   r0,  #1
            mcr   p15, #0, r0, c9, c12, #5 ; select counter
            mov   r0,  #0x11
            mcr   p15, #0, r0, c9, c13, #1 ; select event
            ; select counter 2 event
    		mov   r0,  #2
            mcr   p15, #0, r0, c9, c12, #5 ; select counter
            mov   r0,  #0x11
            mcr   p15, #0, r0, c9, c13, #1 ; select event
            ldmfd sp!, {r0}
            bx    lr
    
        .endasmfunc
    

  • Hi,Chuck

    Thank you four your reply.

    You described "write b00000 in the PMNXSEL register, you will be working with EVTSEL0 and PMC0".
    Is it impossible to count three counters at the same time ?

    Best Regards.
  • Hello Arriy,

    No. Monitoring three events and three counters is absolutely possible. Think of the PMNXSEL register as an address extension where the content plus the 32bit address of the register define the access to the register. So you would write to the PMNXSEL to select the event register; 0,1, or 2; then write to the event register to select the event for the prescribed monitoring channel. Then to read the count you would, again, write to the PMNXSEL register (if changed) to read the count of events in the PMCx register as well.

    If you look at the assembly code I provided as an example, you will see that it selects the counter then selects the event for that counter. It does this three times starting with the value b00000 in PMNXSEL and ending with b00010 in PMNXSEL. So each EVTSEL[0-2] register is initialized with a specified event. When ready to read the counters, you would do the similar steps to initialize the counter and then read the performance monitor count registers, PMC[0-2]
  • Hello,Chuck.

    "Monitoring three events and three counters is absolutely possible" is I can not understand it clearly.
    For exanple, when I select counter 0 by Performance Counter Selection Register(PMNXSEL) register,
    counter 1 and counter 2 counted at the same time ???


    Best Regards.
  • Arriy,

    There are 3 pairs of registers here that we are concerned with. 3 EVTSEL registers and 3 PMC registers. Think of the PMNXSEL as a mux input that enables writing/reading each of the 3 pairs.  i.e., whenever you are configuring EVTSEL0 you have to first set PMNXSEL to b00000 first then write to the CP15_EVENT_SELECTION register. When you want to then configure EVTSEL1 you have to write PMNXWEL to b00001 first then write to CP15_EVENT_SELECTION register, etc. For clarity, i've created the following diagram that is a generic representation of how this works in regard to access to the register( teh diagram is not accurate with respect to the real hardware implementation and intended solely for explanation through a representative format).

    So, as can be seen, the PMNXSEL simply controls/gates access to the registers for reading and writing. Once initialized the PMU will act on all three register sets. I believe there are provisions for configuring and enabling the PMU within Halcogen as well if you want example code on how it works.

  • Hello Chuck
    Thanks to your advice is become easy understand.
    I can understood register operation way.

    I added figure what I would like to ask.

    1. Use the PMNXSEL to set the events the EVTSEL0 and EVTSEL1 and EVTSEL2, respectively.
    2.PMNXSEL is "b00010".This is Lastly set value.
    3.At that time PMC 0, PMC 1, and PMC 2 are also counted?

    Best Regards

  • Hello Arriy,

    Yes. Even if only PMC2 is selected by PMNXSEL register, the other counters will continue to be updated in the background if enabled and configured. The PMNXSEL register is simply a method to address each of the registers for reading and writing during setup.