TMS570LS3137: About ETH12 Ethernet Physical Layer Fault

Hello,

I need to check with my associates on this and will get back to you tomorrow.

This is just a friendly reminder that I’m waiting for your reply.

Thanks for the reminder. I am still awaiting an answer from an internal expert and will get back to you as soon as I have more information regarding the use of the physical layer fault and any associated interrupt.

I can offer, however, that the physical layer fault does not provide an ESM flag and that the group 1, channel 43 ESM flag is not related to a physical layer fault. The ESM GR1, channel 43 flag means that the EMAC master will generate an error signal onto the ESM when it receives an error response from the slave. For example, if the EMAC DMA is reading from the SRAM and the SRAM replies with an error response.

Hello,

Again, apologies for the delay in getting back to you. Our expert on this topic was away on business travel and was only recently able to respond to my question.

This specific diagnostic ties to the ability of the MDIO to detect a lack of response from the PHY. Upon detection, bit 19 (FAULT) of the MDIO Control Register (CONTROL) is set. More information on this bit can be read in section 29.4.2 of the technical reference manual, spns499b.pdf.