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TMS570LS3137: Trace instruction possibility on the 32-bit ETM data bus

Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN,

I have doubts about possibility of instruction tracing on the TMS570LS31 Hercules™ Development Kit. The doubts come from my little experience with configuring TPIU register (see error -1170 forum thread). I found that it is impossible to write and even read the Current Port Size Register (offset 0x004) and by default it is set after reset to 0x00000001 (bus width). I know this from the 8.6.2 chapter of CoreSight Components Technical Reference Manual and from the behavior observed on the digital analyzer connected to the MIPI60 port. When I enable the TPIU Pattern Generator for generating then I observe that:

  • for walking 1's pattern the ETMDATA[0] has 3.3V other pins are grounded
  • for walking 0's pattern all pins are grounded
  • for AA/55 pattern and FF/00 pattern only the ETMDATA[0] alternates each cycle like the clock

Could anybody confirm this?

Regards, Radek

  • Hello Radoslaw,

    So the issue you are seeing iwth the patterns is due to the width of the port that is configured to 1-bit on reset. To see the full results that you want you would need to set the port size to 32-bit.

    From your other post/thread ( error -1170 ) you were unable to access the Port Size register to re-configure it. In fact, you stated that this was the source of the exception that was causing the error. So, this is the root of the problem in both cases. Have you made sure that you are in the correct device mode (privilege mode) and that any MPU settings allow access to the register? Also, I didn't see your write to the Debug access key to enable access in your code listing in the other post. You have to unlock the Coresight Debug access before trying to read from it. I do see that you have the #defines for the access key register and for the key value but no use of it within your code.

  • Hi Chuck,

    Thanks for interesting my problem.

    I've checked device mode and it is System mode (the M bits are set to b11111 in CPSR). I also use the key to enable access to the TPIU registers. In the Halcogen configuration tool it was set for the 10th region (address pool 0xFF000000-0xFFFFFFFF) the Read and Write permission.

    I even tried disabled the MPU.

    I found that access to other TPIU registers, with offsets of 0x204 (Current test pattern/mode) and 0x208 (Test pattern repeat counter), cause also the -1170 DAP error. A couple days earlier I tried to turn on ETM to trace all the memory by the following steps:

    To trace all memory:
    • set bit [24] in register 0x009, the ETMTECR1, to 1
    • set all other bits in register 0x009, the ETMTECR1, to 0
    • set all bits in register 0x007, the ETMTECR2, to 0
    • set register 0x008, the ETMTEEVR, to 0x6F (TRUE).

    but without success. After such experiment I've lost access to TPIU register with 0x204 offset (Current test pattern/mode). I know this because earlier I could set pattern generator to toggle ETMDATA[0] pin.

    It is possible to waste access to register?

  • Hi Radek,

    Just a question at a higher level - what are you planning to do w. the data that comes out of ETM? It's compressed data and there is a pretty sophisticated body of software that is needed to post-process and decompress it. So just capturing the raw data may not tell you that much at least about instruction flow.

    Have you tried a tool like the 'processors.wiki.ti.com/.../XDS_Pro_Trace' It configures all of the registers for you so you just 'turn on' trace in the GUI without worrying about the register writes.
  • Hi Anthony,

    Five years ago I heard about hardware support for instruction monitor specified by the ARM Coresight. Three years later I had a pleasure to work with the Hercules board. During the work I noticed the MIPI60 socket and the connected ETMDATA pins of TMS570 and have started to think about acquiring instruction trace. For my work it is important to know which fragment of code is executed and which not, to produce reliable code. I do not want to buy an expensive specific tool for such purpose in each project because other debug technics are used instead. I want to discover possibilities of ARM Embedded Trace Macrocells by own simple adapter and logic analyzer. Could you explain why I have problems with access to some TPIU registers?

    Best regards,
    Radek
  • Hi Radek,

    Unfortunately we don't have any sort of appnote or documentation that shows how to do this; it's normally handled by the tool that was created by an expert in the subject; and the 'steps' to do this isn't in any sort of human readable format like an XML file you could study --- as far as I know the steps are compiled in the emulation DLL.
  • I have noticed that the external synchronous abort data exception occurs during reading Current Port Size TPIU register (0xFFA03004 address). This may happen when the peripheral register is accessed by the AXI master port of the processor. In such case AXI slave may response with the SLVERR error (for example when exclusive access is made in cortex-R4).

    Could anybody confirm this?
  • I found the answer for my problem with the access to TPIU registers :)
    The answer is in TMS570LS3137 (SPNS162C –APRIL 2012–REVISED APRIL 2015) datasheet document under 6.21.7.1 chapter. There is written the following important information: "Before you begin accessing TPIU registers, TPIU should be unlocked via coresight key and 1 or 2 should be written to this register.", "The address of this register is TPIU base address + 0x404". It means to have access to all TPIU registers (especially registers from the control of TPIU serializer or pattern generator) you should set the clock for them.