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RM57L843: issue with circular buffer using DMA and dummy channel

Part Number: RM57L843

Hi,

a customer has used other e2e posts successfully to implement a circular buffer with DMA and a dummy channel

The customer is trying to use the DMA on the RM57 to fill a circular buffer with data received from the SCI. The E2E site was very helpful, and answers there got him most of the way; now just down to one problem that if solved should allow everything to work.

Here is the setup:

    • Set up 3 DMA channels:
      • RX channel that fills a large (1KiB) buffer, with auto-initiation and BTC enabled. Frame transfer mode is used, with frames of 1 byte triggered by the SCI DMA HW request. Port B read, Port A write.
      • "dummy" channel that  is software-triggered and makes a transfer of one word from an arbitrary peripheral register (I picked the DMA PTCRL register, but the result isn't used). This channel is used to force arbitration. Port B read, Port A write.
      • "sentinel" channel that is hardware-triggered by the same request as the RX channel. Transfers 1 byte between arbitrary locations. The enable bit of this channel is manipulated in such a way that it on the first frame of the RX block, and then is not triggered until the buffer wraps around.
    • Set up BTC interrupts for each channel:
      • The RX channel BTC clears the "transfer in progress" flag, and checks for overflows.
      • The dummy BTC reads the Working Control Packet for the RX channel and stores the CFTCOUNT field so the application knows how far it can safely read. It also does additional overflow checking.
      •  The sentinel BTC sets the "transfer in progress" flag so the dummy BTC can tell whether an arbitration was triggered; it is possible that the buffer has filled, in which case no arbitration will be triggered and the CFTCOUNT will not be written back to the WCP. In this case the application needs to know it cannot read past the end of the buffer.

Tested the setup by sending a sequence of bytes from my PC and checking that the sequence received matched the sequence sent. It works perfectly, except in one condition: When the dummy channel transfer occurs at a byte boundary on the SCI (so that the last byte ends and the next one starts while the dummy transfer is in progress), the DMA stops updating the WCP. Thereafter, CFTCOUNT is frozen and no longer updated, so the application can no longer tell how much data is in the buffer.

 

 The customer is not sure what causes this behavior, but they assume it has something to do with the DMA state machine. Any suggestions are greatly appreciated!

Regards,

--Gunter

  • Gunter,

    So I don't understand this method fully except that from the original post it seems the idea is to force an arbitration and therefore force a writeback of the control packet to the DMA's memory.

    I'm not sure how that would behave differently on the RM57 because unlike the RM46,  the RM57 DMA has been upgraded.

    Here's a block diagram from the RM46 manual:

     

    Compare with this block diagram from the RM57 manual:

    See how there are two parallel FIFOs and ports on the DMA of the RM57?


    My instinct says this might be messing with some otherwise critical timing that made the scenario work on RM46 but maybe it has a hazard on RM57.


    Or maybe the hazard is there on RM46 too and the original post didn't see it.


    I don't know the actual answer but the chip really was not designed with this feature in mind.   There isn't a reliable way to force the write back of the control packet such that it can be read  'mid flight' by software.   At least not one that was planned for.


    This is definitely one shortcoming of the integration of SCI and DMA on this device.

  • Hi Anthony,

    Gunter posted this question on my behalf. I understand that I'm operating at (or past) the edge of what the system's designed to do, but I was able to ultimately get it working! I ended up ditching the sentinel channel, and reconfiguring the dummy channel: Now it is chained to the RX channel, and it transfers the CTCOUNT register from the SCI RX channel into a location in RAM after every frame received. I'm sure it affects the performance of the DMA, but I've tested it and found that it works fine for our needs.

    Thanks for all the help,
    Trevor