Information Redundancy Techniques - We are considering adopting L2 / L3 Interconnect Specific.
I do not know the peripheral connected to L2 / L3.
Specifically, which peripheral are covered with L2 / L3 interconnect?
So please refer to the device datasheet SPNS162 in section 6.5.1 the L1 and L2 are defined with respect to the CPU.
Then refer to section 2.1.1 of SPNU499 where the bus architecture is drawn.
I have marked up what I would consider L2 and L3, drawing the line mainly based on the type of interconnect.
But it doesn't really matter since you need the union of everything connected to L2,L3 so that is everything except for L1...
Also note that by including the 'PCR' in the purple box I mean to include that line connecting to all the peripherals on the bottom of the page.
Actually that isn't a shared bus .. each peripheral has it's own connection to a port on that PCR... so the PCR is the actual interconnect.
Anyway all those boxes on the bottom of the figure are peripherals on L3..
