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CCS/TMS570LC4357: Clearing the contents of the data and instruction cache

Caroline Brown
Prodigy 20 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

Hello,

I am trying to run simulations of an FFT algorithm on the processor by putting the function in a for loop.

I am measuring cache misses using a counter on the PMU, this works correctly for iteration one however following iterations always display zero data misses. I was wondering if there was a simple way to clear the cache contents on each iteration of the for loop?

Thanks,

Caroline

  • 0
    TI__Guru 68070 points
    Hi Caroline,

    Is it actually possible that there are zero data misses because after the first iteration your dataset is held in the cache?

    You can change the MPU type to non cachable for the area where your FFT data is stored, and this will always cause the processor to go to memory for data.

    You can also disable the cache but there is only one checkbox for that in HalCoGen and it will disable both the instruction and data cache so you will get a more severe slowdown than just missing the data cache by itself would give you.

    Best Regards,
    Anthony
  • 0 in reply to Anthony F. Seely
    Prodigy 20 points
    Hi Anthony,

    Thanks for your response! I don't think I explained myself very well, I'm assuming that the readouts are correct and there are zero cache misses however I want each iteration to be comparable on the number of data and instruction cache misses. Therefore at the start of each iteration I want to clear the cache so it will have the same number, or similar, misses as the first iteration (I'm measuring the cache predictability and it'll save me time to have it in a loop rather than re-load the program each time).

    I will then run the program with the cache disabled and compare the performance to when the cache is used.

    I hope that explains it better? I feel like there must be some way to clear the cache contents, I've seen you can invalidate the contents but I'm not entirely sure that's what I want to be doing.

    Thanks,
    Caroline
  • 0 in reply to Caroline Brown
    TI__Guru 68070 points
    Hi Caroline,

    Sure you can do that too; if that's what you want to do.

    The best resource for the core and caches is:

    "ARM® Cortex®-R Series Version: 1.0 Programmer’s Guide" which is a document from ARM Ltd. ARM DEN 0042A

    There is a section '7.7 Invalidating and cleaning cache memory' that should explain what to do.

    You also need to have the CPU reference manual so you know which CP15 registers to write.

    There are two functions in HalCoGen 'HL_sys_core.asm'

    _dCacheInvalidate_, _iCacheInvalidate_

    although I can't tell you personally if they work or not (assume they do; but haven't used them myself).

    Best Regards,
    -Anthony