TM4C1294NCPDT: TM4C129X SPI communication with ADS1243 ADC

Kiran Shingote8

Prodigy 250 points

Part Number: TM4C1294NCPDT
Other Parts Discussed in Thread: ADS1243

I am using my own TM4C1294NCPDT board and connected Micro SD card, Flash MX66L51235FZ2I and ADS1243 to SSI3 port.

I am using Slave select pins PE1 for SD card, PQ1 for Flash and PK4 for ADS1243.

Getting clock while communicating with SD card flash but not with ADS1243.

Also tested SD card read operation and Flash read and write operation, they are working fine.

Not able to communicate or generate clock and Tx signals at particular pins while communicating ADS1243.

Here I am attaching code to read ADC count. I have done ADC communication with LM3S9B96 using SSI0 using same init and read procedure.

Can any one help to solve this problem

//------------------------------------- INIT ADC --------------------------------------------
uint32_t a_SSIRecByte[4];
uint32_t a_SSISendByte[4];

unsigned long uiCount;

void init_adc()
{
ROM_GPIOPinWrite(GPIO_PORTK_BASE,ADS1243,ADS1243_ENABLE);
delay_ms(5);

a_SSISendByte[0] = 0xFE;
adc_ssi_write(a_SSISendByte,1);
delay(10);

a_SSISendByte[0] = 0xFC;
adc_ssi_write(a_SSISendByte,1);
delay(10);

a_SSISendByte[0] = 0x50;
a_SSISendByte[1] = 0x00;
a_SSISendByte[2] = 0x00;
adc_ssi_write(a_SSISendByte,3);
delay(10);

a_SSISendByte[0] = 0x52;
a_SSISendByte[1] = 0x00;
a_SSISendByte[2] = 0xC2;
adc_ssi_write(a_SSISendByte,3);
delay(10);

a_SSISendByte[0] = 0xF0;
adc_ssi_write(a_SSISendByte,1);
delay(10);

delay_ms(250);
delay(2);

a_SSISendByte[0] = 0x51;
a_SSISendByte[1] = 0x00;
a_SSISendByte[2] = 0x05;
adc_ssi_write(a_SSISendByte,3);
delay_ms(5);

ROM_GPIOPinWrite(GPIO_PORTK_BASE,ADS1243,ADS1243_DISABLE);
}

//------------------------------------- READ ADC --------------------------------------------

unsigned int read_adc(unsigned char ucChannelNo)
{
unsigned long ulRead;
ROM_GPIOPinWrite(GPIO_PORTK_BASE,ADS1243,ADS1243_ENABLE);
delay_ms(5);

do
{
ulRead = ROM_GPIOPinRead(GPIO_PORTK_BASE, ADS1243_DRDY);
}while(ulRead != 0x00000000);

a_SSISendByte[0] = 0x51;
a_SSISendByte[1] = 0x00;
a_SSISendByte[2] = ucChannelNo;
adc_ssi_write(a_SSISendByte,3);

delay(10);
a_SSISendByte[0] = 0x01;
adc_ssi_write(a_SSISendByte,1);

adc_ssi_read(a_SSIRecByte,3);

uiCount = 0;
uiCount = a_SSIRecByte[0] * 256;
uiCount = uiCount + a_SSIRecByte[1];
delay_ms(5);

ROM_GPIOPinWrite(GPIO_PORTK_BASE,ADS1243,ADS1243_DISABLE);

return(uiCount);
}

//------------------------------------- WRITE DATA SSI --------------------------------------------

void adc_ssi_write(uint32_t *ucData, unsigned short usLen)
{
unsigned long ulLoop = 0;;
uint32_t ulDummy;

SSIAdvModeSet(SSI3_BASE,SSI_ADV_MODE_WRITE);
SSIAdvFrameHoldEnable(SSI3_BASE);
if(usLen == 3)
{
SSIDataPut(SSI3_BASE,ucData[ulLoop]);
SSIDataGet(SSI3_BASE,&ulDummy);
ulLoop++;
SSIDataPut(SSI3_BASE,ucData[ulLoop]);
SSIDataGet(SSI3_BASE,&ulDummy);
ulLoop++;
SSIAdvDataPutFrameEnd(SSI3_BASE,ucData[ulLoop]);
SSIDataGet(SSI3_BASE,&ulDummy);
}
else
{
SSIAdvDataPutFrameEnd(SSI3_BASE,ucData[ulLoop]);
SSIDataGet(SSI3_BASE,&ulDummy);
}
}

//------------------------------------- READ DATA SSI --------------------------------------------

void adc_ssi_read(uint32_t *ucData, unsigned long ulLen)
{
uint32_t ulData;
unsigned long ulLoop = 0;

SSIAdvModeSet(SSI3_BASE,SSI_ADV_MODE_READ_WRITE);

SSIDataPut(SSI3_BASE,0x00);
SSIDataGet(SSI3_BASE,&ulData);
ucData[ulLoop] = (ulData);
ulLoop++;

SSIAdvDataPutFrameEnd(SSI3_BASE,0x00);
SSIDataGet(SSI3_BASE,&ulData);
ucData[ulLoop] = (ulData);
}

//------------------------------------- INIT SSI--------------------------------------------

extern unsigned char a_ASCII[10];

uint8_t g_ui8InstrReadID[] = {0x90,0x00,0x00,0x00};
uint32_t pui32DataTx[NUM_SSI_DATA];
uint32_t pui32DataRx[NUM_SSI_DATA];
uint32_t ui32DeviceID;

void ssi_flash_init(uint32_t ui32SysClock)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);

//
// Configure and enable the SSI port for SPI master mode. Use SSI3,
// system clock supply, idle clock level low and active low clock in
// freescale SPI mode, master mode, 1MHz SSI frequency, and 8-bit data.
// For SPI mode, you can set the polarity of the SSI clock when the SSI
// unit is idle. You can also configure what clock edge you want to
// capture data on. Please reference the datasheet for more information on
// the different SPI modes.
//
SSIConfigSetExpClk(SSI3_BASE, ui32SysClock, SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 1000000, 8);

//
// Enable the SSI3 module.
//
SSIAdvModeSet(SSI3_BASE,SSI_ADV_MODE_WRITE);
SSIAdvFrameHoldEnable(SSI3_BASE);
SSIEnable(SSI3_BASE);

//
// First Read the DEVICE ID
//

ROM_GPIOPinWrite(GPIO_PORTQ_BASE, FLASH, FLASH_ENABLE);

ui32DeviceID = SSILibSendReadIDAdvMode(SSI3_BASE);
if(ui32DeviceID != 0xC219) UARTSend("No External Flash\n",COM0);
else UARTSend("External Flash Detected \n",COM0);

ROM_GPIOPinWrite(GPIO_PORTQ_BASE, FLASH, FLASH_DISABLE);
}

//------------------------------------- TEST FLASH --------------------------------------------
void test_flash()
{
unsigned char i,ucCount;
uint32_t pui32Dummy[1];
uint32_t ui32Index;

//
// Loop forever, processing the on-screen animation. All other work is
// done in the interrupt handlers.
//
//
// Read any residual data from the SSI port. This makes sure the receive
// FIFOs are empty, so we don't read any unwanted junk. This is done here
// because the SPI SSI mode is full-duplex, which allows you to send and
// receive at the same time. The SSIDataGetNonBlocking function returns
// "true" when data was returned, and "false" when no data was returned.
// The "non-blocking" function checks if there is any data in the receive
// FIFO and does not "hang" if there isn't.
//
while(SSIDataGetNonBlocking(SSI3_BASE, &pui32Dummy[0]))
{
}

//
// Initialize the Transmit Buffer
//
ucCount = 1;
for(ui32Index=0;ui32Index<NUM_SSI_DATA;ui32Index++)
{
pui32DataTx[ui32Index] = ucCount;
pui32DataRx[ui32Index] = 0x0;
ucCount++;
}
UARTSend("Starting Read Operations...\n",COM4);
SSILibSendReadDataAdvBi(SSI3_BASE,0x0,INS_READ_DATA);
for(ui32Index=0;ui32Index<NUM_SSI_DATA-1;ui32Index++)
{
SSIDataPut(SSI3_BASE,DUMMY_BYTE);
SSIDataGet(SSI3_BASE,&pui32DataRx[ui32Index]);
}
SSIAdvDataPutFrameEnd(SSI3_BASE,DUMMY_BYTE);
SSIDataGet(SSI3_BASE,&pui32DataRx[NUM_SSI_DATA-1]);
UARTSend("Read Completed...\n",COM4);

//
// Display Data
//
for(ui32Index=0;ui32Index<NUM_SSI_DATA;ui32Index++)
{
decimal_to_ascii(pui32DataRx[ui32Index],3);
for(i=0;i<3;i++)
{
UARTCharPut(UART0_BASE,a_ASCII[i]);
}
UARTCharPut(UART0_BASE,10);
UARTCharPut(UART0_BASE,13);
}
}

//---------------------------------PIN CONFIGURATION ------------------------

void init_pinconfig()
{
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);

// GPIO_PORTA_AHB_DIR_R |= 0xC8; // Port A
// GPIO_PORTA_AHB_DEN_R |= 0xFC;
/*
GPIO_PORTB_AHB_DIR_R |= 0x34; // Port B
GPIO_PORTB_AHB_DEN_R |= 0x37;

GPIO_PORTC_AHB_DIR_R |= 0x30; // Port C
GPIO_PORTC_AHB_DEN_R |= 0x30;

GPIO_PORTD_AHB_DIR_R |= 0x60; // Port D
GPIO_PORTD_AHB_DEN_R |= 0xFF;

GPIO_PORTE_AHB_DIR_R |= 0x3C; // Port E
GPIO_PORTE_AHB_DEN_R |= 0x3D;

GPIO_PORTF_AHB_DIR_R |= 0x0C; // Port F
GPIO_PORTF_AHB_DEN_R |= 0x0D;

GPIO_PORTG_AHB_DIR_R |= 0x01; // Port G
GPIO_PORTG_AHB_DEN_R |= 0x03;

GPIO_PORTH_AHB_DIR_R |= 0x00; // Port H
GPIO_PORTH_AHB_DEN_R |= 0x0F;

GPIO_PORTJ_AHB_DIR_R |= 0x02; // Port J
GPIO_PORTJ_AHB_DEN_R |= 0x03;

GPIO_PORTK_DIR_R |= 0x9F; // Port K
GPIO_PORTK_DEN_R |= 0xFF;

GPIO_PORTL_DIR_R |= 0x00; // Port L
GPIO_PORTL_DEN_R |= 0xC0;

GPIO_PORTM_DIR_R = 0xFF; // Port M
GPIO_PORTM_DEN_R = 0xFF;

GPIO_PORTN_DIR_R |= 0x3D; // Port N
GPIO_PORTN_DEN_R |= 0x3F;

GPIO_PORTP_DIR_R |= 0x04; // Port P
GPIO_PORTP_DEN_R |= 0x04;
*/

// GPIO_PORTQ_DIR_R |= 0x17; // Port Q
// GPIO_PORTQ_DEN_R |= 0x1F;

/*
ROM_GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_3); // DIN 1

ROM_GPIOPinTypeGPIOOutput(GPIO_PORTQ_BASE, GPIO_PIN_4); // Wifi Power Enable
ROM_GPIOPinWrite(GPIO_PORTQ_BASE, GPIO_PIN_4, GPIO_PIN_4); // Wifi Power Enable

delay_ms(1);

ROM_GPIOPinWrite(GPIO_PORTB_BASE, GPS, GPS_ON); //GPS supply enable

ROM_GPIOPinWrite(GPIO_PORTN_BASE, SDI12, SDI12_DISABLE);
*/
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_7);
ROM_GPIOPinWrite(GPIO_PORTK_BASE, ADC_PWR, ADC_ON); // ADC power enable
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_4);
ROM_GPIOPinWrite(GPIO_PORTK_BASE, ADS1243, ADS1243_DISABLE);// ADS1243 Disable
ROM_GPIOPinTypeGPIOInput(GPIO_PORTK_BASE, GPIO_PIN_5); // DRDY
/*
ROM_GPIOPinWrite(GPIO_PORTQ_BASE, WIFI, WIFI_ON); // Wifi module power enable

ROM_GPIOPinWrite(GPIO_PORTB_BASE, ICDI, ICDI_ON); // ICDI power enable

ROM_GPIOPinWrite(GPIO_PORTA_BASE, LCD, LCD_ON); // LCD Module enable

ROM_GPIOPinWrite(GPIO_PORTP_BASE, RS485, RS485_ON); // 5V Power enable
ROM_GPIOPinWrite(GPIO_PORTN_BASE, RS485, RS485_RX_ENABLE); // RS485 RX Enable
*/
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_5);
ROM_GPIOPinWrite(GPIO_PORTE_BASE, FLASH_PWR, FLASH_ON); // Enable Flash Supply

ROM_GPIOPinTypeGPIOOutput(GPIO_PORTQ_BASE, GPIO_PIN_1); // SSI3-CEMX66L51235F
ROM_GPIOPinWrite(GPIO_PORTQ_BASE, FLASH, FLASH_DISABLE); // MX66 Disable

ROM_GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_1); // SD card CE
ROM_GPIOPinWrite(GPIO_PORTE_BASE, SD_CARD, SD_CARD_DISABLE);// SD card CE

ROM_GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_4); //
ROM_GPIOPinWrite(GPIO_PORTE_BASE, LED, LED_OFF); // User LED

/*
* // USB
HWREG(GPIO_PORTD_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
HWREG(GPIO_PORTD_BASE + GPIO_O_CR) = 0xff;

ROM_GPIOPinConfigure(GPIO_PD6_USB0EPEN);
ROM_GPIOPinConfigure(GPIO_PD7_USB0PFLT);
ROM_GPIOPinTypeUSBAnalog(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1);
ROM_GPIOPinTypeUSBDigital(GPIO_PORTD_BASE, GPIO_PIN_6 | GPIO_PIN_7);
ROM_GPIOPinTypeUSBAnalog(GPIO_PORTL_BASE, GPIO_PIN_6 | GPIO_PIN_7);
*/
// Flash and SD card
HWREG(GPIO_PORTF_BASE+GPIO_O_LOCK) = GPIO_LOCK_KEY;
HWREG(GPIO_PORTF_BASE+GPIO_O_CR) |= GPIO_PIN_0;

ROM_GPIOPinConfigure(GPIO_PQ0_SSI3CLK);
ROM_GPIOPinConfigure(GPIO_PQ2_SSI3XDAT0);
ROM_GPIOPinConfigure(GPIO_PF0_SSI3XDAT1);

ROM_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_0);
ROM_GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_0 | GPIO_PIN_2);
}

//-----------------------------MAIN FUNCTION ------------------------------
int main(void)
{
int nStatus;

FRESULT iFResult;
int result;
//
// Run from the PLL at 120 MHz.
//
g_ui32SysClock = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), 120000000);

//
// Configure the device pins.
//
init_pinconfig();

delay_ms(10);
uart0_init(g_ui32SysClock);
delay_ms(100);

if((CH1.Averaging <= 0) || (CH1.Averaging > 50)) CH1.Averaging = 5;
if((CH2.Averaging <= 0) || (CH2.Averaging > 50)) CH2.Averaging = 5;
if((CH3.Averaging <= 0) || (CH3.Averaging > 50)) CH3.Averaging = 5;
if((CH4.Averaging <= 0) || (CH4.Averaging > 50)) CH4.Averaging = 5;

timer0_init(g_ui32SysClock);

/*
UARTSend("mount\n",COM0);
iFResult = f_mount(0, &g_sFatFs);
if(iFResult != FR_OK)
{

return(1);
}

result = Cmd_cat(argc1, argv1[1]);*/

//--------------------------------------------------------------------

UARTSend("Flash init\n",COM0);
ssi_flash_init(g_ui32SysClock);
UARTSend("Flash Test\n",COM0);
// test_flash1();
UARTSend("ADC INIT\n",COM0);
init_adc();
UARTSend("ADC Test\n",COM0);

/*
//------------------------USB TEST-----------------------------------
usb_init(g_ui32SysClock);
delay_ms(1);
//--------------------------------------------------------------------
*/

while(1)
{

if(bInterval)
{
bInterval = 0;
ucChannelNo++;
if(ucChannelNo > 5) ucChannelNo = 1;
}
averaging();

decimal_to_ascii(a_Adc[1],5);
a_ASCII[5] = 0;
UARTSend(a_ASCII,COM0);
UARTCharPut(UART0_BASE,' ');

decimal_to_ascii(a_Adc[2],5);
a_ASCII[5] = 0;
UARTSend(a_ASCII,COM0);
UARTCharPut(UART0_BASE,' ');

decimal_to_ascii(a_Adc[3],5);
a_ASCII[5] = 0;
UARTSend(a_ASCII,COM0);
UARTCharPut(UART0_BASE,' ');

decimal_to_ascii(a_Adc[4],5);
a_ASCII[5] = 0;
UARTSend(a_ASCII,COM0);
UARTCharPut(UART0_BASE,' ');

decimal_to_ascii(a_Adc[5],5);
a_ASCII[5] = 0;
UARTSend(a_ASCII,COM0);
UARTCharPut(UART0_BASE,'\n');
delay_ms(400);

}

}

//-------------------- TIMER 0 Interrupt ---------------------

// The interrupt handler for the first timer interrupt.

void Timer0IntHandler(void)
{
//
// Clear the timer interrupt.
//
ROM_TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);

//
// Update the interrupt status on the display.
//
ROM_IntMasterDisable();

if(ucToggle0)
{
GPIO_PORTE_AHB_DATA_R |= 0x10;
}
else
{
GPIO_PORTE_AHB_DATA_R &= ~(0x10);
}
ucToggle0 = ~ucToggle0;

ucScrollCounter++;
if(ucScrollCounter >= 6)
{
ucScrollCounter = 0;
ucMessageCounter++;
bInterval = 1;
// bDisplayOnce = 0;
if(ucMessageCounter > TOTAL_MESSAGES)
{
ucMessageCounter = 1;
// bOneCycleDelay = 1;
}
}
ROM_IntMasterEnable();
}

over 8 years ago

0 Bob Crosby over 8 years ago

TI__Guru 72500 points

It looks like you are using the ssi_flash_init() routine to initialize SSI3, then using GPIO PQ1 and PK1 and manually selecting the flash or the ADC. I don't see what the routine SSILibSendReadDataAdvBi() function is doing. Are you putting SSI3 in a "read 2-bit wide" mode? If so, do you put it back in legacy mode for the ADC?

0 Kiran Shingote8 over 8 years ago in reply to Bob Crosby

Prodigy 250 points

Hi Bob,

After working for 4 days following code worked successfully. There was problem with signal timings

But this code works for 25KHz and less frequency. I want to do at 1MHz.

//----------------------------------------------------------------------------
uint32_t a_SSIRecByte[4];
uint32_t a_SSISendByte[4];

unsigned int uiCount;

void init_adc(uint32_t ui32SysClock, unsigned char ucChannel)
{
SSIConfigSetExpClk(SSI3_BASE, ui32SysClock, SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 25000, 8);

SSIAdvModeSet(SSI3_BASE,SSI_ADV_MODE_LEGACY);
SSIEnable(SSI3_BASE);

ucChannel = ucChannel - 1;
ucChannel = (ucChannel << 4) + 0x07;

a_SSISendByte[0] = (0xFE); // Reset
adc_ssi_write(a_SSISendByte,1);
delay_ms(50);

a_SSISendByte[0] = (0xFC); //Sync Command
adc_ssi_write(a_SSISendByte,1);

a_SSISendByte[0] = (0xF0); //Self Cal
adc_ssi_write(a_SSISendByte,1);

a_SSISendByte[0] = (0x50); //Write 0th address
a_SSISendByte[1] = (0x00);
a_SSISendByte[2] = (0x00); //Setup register
adc_ssi_write(a_SSISendByte,3);

a_SSISendByte[0] = (0x52); //Write 2nd address
a_SSISendByte[1] = (0x00);
a_SSISendByte[2] = (0xC0); //ACR 0xC2
adc_ssi_write(a_SSISendByte,3);

a_SSISendByte[0] = (0x51); //Write 1st address
a_SSISendByte[1] = (0x00);
a_SSISendByte[2] = (ucChannel); //0x05 //MUX register
adc_ssi_write(a_SSISendByte,3);
}

unsigned int read_adc(unsigned char ucChannel)
{
unsigned long ulRead;

SSIAdvModeSet(SSI3_BASE,SSI_ADV_MODE_LEGACY);
SSIEnable(SSI3_BASE);

do
{
ulRead = ROM_GPIOPinRead(GPIO_PORTK_BASE, ADS1243_DRDY);
}while(ulRead != 0x00000000);

a_SSISendByte[0] = (0x51); //Write 1st address
a_SSISendByte[1] = (0x00);
a_SSISendByte[2] = (ucChannel); //MUX register 07 to 47
adc_ssi_write(a_SSISendByte,3);

a_SSISendByte[0] = (0x01); // Read Data command
adc_ssi_write(a_SSISendByte,1);
delay_ms(1);

adc_ssi_read(a_SSIRecByte,3);

uiCount = 0;
uiCount = a_SSIRecByte[0] * 256;
uiCount = uiCount + a_SSIRecByte[1];

return(uiCount);
}

void adc_ssi_write(uint32_t *ucData, unsigned short usLen)
{
unsigned long ulLoop = 0;
uint32_t ulDummy;

ulLoop = 0;
ROM_GPIOPinWrite(GPIO_PORTK_BASE,ADS1243,ADS1243_ENABLE);
SSIDataPut(SSI3_BASE,ucData[0]);
SSIDataGet(SSI3_BASE,&ulDummy);

if(usLen == 3)
{
SSIDataPut(SSI3_BASE,ucData[1]);
SSIDataGet(SSI3_BASE,&ulDummy);

SSIDataPut(SSI3_BASE,ucData[2]);
SSIDataGet(SSI3_BASE,&ulDummy);
ROM_GPIOPinWrite(GPIO_PORTK_BASE,ADS1243,ADS1243_DISABLE);
}
}

void adc_ssi_read(uint32_t *ucData, unsigned long ulLen)
{
ROM_GPIOPinWrite(GPIO_PORTK_BASE,ADS1243,ADS1243_ENABLE);
SSIDataPut(SSI3_BASE,0x55);
SSIDataGet(SSI3_BASE,&ucData[0]);

SSIDataPut(SSI3_BASE,0x55);
SSIDataGet(SSI3_BASE,&ucData[1]);

SSIDataPut(SSI3_BASE,0x55);
SSIDataGet(SSI3_BASE,&ucData[2]);

ROM_GPIOPinWrite(GPIO_PORTK_BASE,ADS1243,ADS1243_DISABLE);
}

Regards,

Kiran

0 Bob Crosby over 8 years ago in reply to Kiran Shingote8

TI__Guru 72500 points

Comparing the SSI requirements of the ADS1243, diagram 1 on page 6 of LINK, it looks to me like you need to use the SSI with SPO=0 and SPH=1. See LINK figure 17-6 on page 1237. That means you should use SSI_FRF_MOTO_MODE_1 in the function SSIConfigSetExpClk. The data comes out on the rising edge of the clock and is sampled on the falling edge.

SSIConfigSetExpClk(SSI3_BASE, ui32SysClock, SSI_FRF_MOTO_MODE_1,SSI_MODE_MASTER, 25000, 8);

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TM4C1294NCPDT: TM4C129X SPI communication with ADS1243 ADC