RM42L432: How does the bit multiplexing scheme implement in TCRAM of RM42L432?

user4693815 said:

(1) How does the bit multiplexing scheme implement in Primary SRAM?

The bit mulitplexing has to do with the architecture of the RAM in relation to physical location of the bit cells. As noted in the paragraph you included in your post, "the bits accessed to generate a logical (CPU) word are not physically adjacent. This scheme helps to reduce the probability of physical multi-bit faults resulting in logical multi-bit faults..."

user4693815 said:

(2)Is the same bit multiplexing scheme for all memory of RM42L432 device?

Each element with SRAM will have it's own unique identifier to indicate if this is also a feature included within the memory for those elements that include RAM. Note section 7.6 and 7.4 also discuss bit multiplexing for specific instances of memory.

user4693815 said:

Fault Avoidance is offered as a test for RAM8 diagnostic.

My question:       What is the meaning of "Fault Avoidance"  here?  And how to certify "Fault Avoidance"?

In general, the safety standards IEC61508 and ISO26262 do not cover the instances of fault avoidance and only refer to faults. In this case and in the case of ECC in general, a mechanism is provided to correct the fault on the fly such that it never impacts the application. Although this does not contribute to the overall diagnostic coverage of the device, it does impact the FIT rate calculations since the fault is avoided. In addition, since the end need for the system is to protect the safety function(s) it serves the end goal of a safety system and; therefore, needs to be included.

user4693815

(1) How does the bit multiplexing scheme implement in Primary SRAM?

The bit mulitplexing has to do with the architecture of the RAM in relation to physical location of the bit cells. As noted in the paragraph you included in your post, "the bits accessed to generate a logical (CPU) word are not physically adjacent. This scheme helps to reduce the probability of physical multi-bit faults resulting in logical multi-bit faults..."

  My question:   " The bit mulitplexing has to do with the architecture of the RAM in relation to physical location of the bit cells."       Where to find the related documents which detail describe architecture of the RAM ? I have read the Data Sheet, Technical Reference Manual and Safety Manual. However ,there is only block level implementation of CPU SRAM.  

user4693815

Fault Avoidance is offered as a test for RAM8 diagnostic.

My question:       What is the meaning of "Fault Avoidance"  here?  And how to certify "Fault Avoidance"

In general, the safety standards IEC61508 and ISO26262 do not cover the instances of fault avoidance and only refer to faults. In this case and in the case of ECC in general, a mechanism is provided to correct the fault on the fly such that it never impacts the application. Although this does not contribute to the overall diagnostic coverage of the device, it does impact the FIT rate calculations since the fault is avoided. In addition, since the end need for the system is to protect the safety function(s) it serves the end goal of a safety system and; therefore, needs to be included.

In this case, the "diagnostic measure" is a fault avoidance mechanism and not categorized as a true diagnostic and. therefore, has no test for diagnostic. It is an architectural implementation of the RAM bit cells. It is automatic in that it is not a SW dependent mechanism that the application can disable or enable. It is similar to the physical diversity of the CPU except that the physical orientation of the lockstep CPUs has no directly quantifiable impact where this physical separation of the bits within a word impacts the probability of a double bit failure and directly impacts the transient FIT rates.