Hi,
for a current project we are using the TM4C123GH6PM uC together with an FPGA. Our plan is to drive clock the FPGA from the uC to have run synchronized. To do that I've connected pin PB5 to the FPGA clock input set it up to work as PWM output M0PWM3. To clock the TM4C123GH6PM we're using the PIOSC and have configured it to run at 80MHz. The PWM module uses the SysCtl (80MHz) and outputs a PWM Signal of 80MHz (50/50).
Now the problem is that when I investigate the PWM signal on the scope everything looks good at the trigger point. But when I look at +2us I already see a jitter of about 7ns. This phenomenon increases over time. Now I've hooked up a Lauchpad (EK-TM4C123GK) to the scope and run the same code. It has the same issue. Ok so far. When I use the external 16 MHz crystal as clock source everything is stable.
I hope anyone can help me on this Topic.
I've pasted the relevent source code and two photos from the scope Investigation below:
// Set the system clock to run at 80Mhz
ROM_SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_OSC_INT);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM0);
//
// Configure the GPIO pin muxing to select PWM03 functions for these pins.
//
ROM_GPIOPinConfigure(GPIO_PB5_M0PWM3);
//
// Configure the PWM function for this pin.
//
ROM_GPIOPinTypePWM(FPGA_GPIO_PORT_BASE, FPGA_CLK_EN_PIN);
//
// Configure the PWM0 to count down without synchronization.
//
PWMGenConfigure(PWM0_BASE, PWM_GEN_1, PWM_GEN_MODE_DOWN);
//
// Set the PWM period to 16MHz. To calculate the appropriate parameter
// use the following equation: N = (1 / f) * SysClk. Where N is the
// function parameter, f is the desired frequency, and SysClk is the
// system clock frequency.
// In this case you get: (1 / 16MHz) * 80MHz = 5 cycles.
//
ROM_PWMGenPeriodSet(PWM0_BASE, PWM_GEN_1, 5);
//
// Set PWM0 to a duty cycle of 50%. You set the duty cycle as a function
// of the period. Since the period was set above, you can use the
// PWMGenPeriodGet() function.
//
ROM_PWMPulseWidthSet(PWM0_BASE, PWM_OUT_3,
ROM_PWMGenPeriodGet(PWM0_BASE, PWM_GEN_1) / 2);
//
// Enable the PWM0 Bit3 (PB5) output signal.
//
ROM_PWMOutputState(PWM0_BASE, PWM_OUT_3_BIT, true);
//
// Enable the PWM generator block.
//
ROM_PWMGenEnable(PWM0_BASE, PWM_GEN_1);
