TM4C1294NCPDT: adc sample rate set and i2c data

Hello Prateek,

1. The ADC clock speed is configured by using the ADCClockConfigSet API call. To set different sampling rates it depends on how you are triggering the ADC. That is something you have not mentioned here.
2. You cannot use ADC0 and ADC1 for Sequencer0. Each ADC has its own sequencer.
3. For I2C issue, you would need to check the functions that are being used to send the data and compare it with the bus value as seen on the scope or a LA. Again there is no code to associate the issues you have.

HI Amit,

1- i have system clock configured by

SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |SYSCTL_OSC_MAIN | SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_480), 120000000);

and DMA Configuration

#define MEM_BUFFER_SIZE 8

static uint32_t g_ui32Src0ABuf[MEM_BUFFER_SIZE];
static uint32_t g_ui32Src0BBuf[MEM_BUFFER_SIZE];
static uint32_t g_ui32Src0ABuf[MEM_BUFFER_SIZE];
static uint32_t g_ui32Src0BBuf[MEM_BUFFER_SIZE]

SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
ADCClockConfigSet(ADC0_BASE,ADC_CLOCK_SRC_ALTCLK | ADC_CLOCK_RATE_FULL,8);
ADCClockConfigSet(ADC1_BASE,ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL,8);
SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);

GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |GPIO_PIN_3);
GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 |GPIO_PIN_7);
GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_4 | GPIO_PIN_5);
GPIOPinTypeADC(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_5);
GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |GPIO_PIN_3);

ADCSequenceStepConfigure(ADC0_BASE, 0, 0, ADC_CTL_CH0 );
ADCSequenceStepConfigure(ADC0_BASE, 0, 1, ADC_CTL_CH1 );
ADCSequenceStepConfigure(ADC0_BASE, 0, 2, ADC_CTL_CH2 );
ADCSequenceStepConfigure(ADC0_BASE, 0, 3, ADC_CTL_CH3 );
ADCSequenceStepConfigure(ADC0_BASE, 0, 4, ADC_CTL_CH4 );
ADCSequenceStepConfigure(ADC0_BASE, 0, 5, ADC_CTL_CH5 );
ADCSequenceStepConfigure(ADC0_BASE, 0, 6, ADC_CTL_CH6 );
ADCSequenceStepConfigure(ADC0_BASE, 0, 7, ADC_CTL_CH7 |  ADC_CTL_END);
ADCSequenceStepConfigure(ADC1_BASE, 0, 0, ADC_CTL_CH8 );
ADCSequenceStepConfigure(ADC1_BASE, 0, 1, ADC_CTL_CH9 );
ADCSequenceStepConfigure(ADC1_BASE, 0, 2, ADC_CTL_CH10);
ADCSequenceStepConfigure(ADC1_BASE, 0, 3, ADC_CTL_CH11);
ADCSequenceStepConfigure(ADC1_BASE, 0, 4, ADC_CTL_CH12);
ADCSequenceStepConfigure(ADC1_BASE, 0, 5, ADC_CTL_CH13);
ADCSequenceStepConfigure(ADC1_BASE, 0, 6, ADC_CTL_CH14);
ADCSequenceStepConfigure(ADC1_BASE, 0, 7, ADC_CTL_CH15 | ADC_CTL_END);

ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_ALWAYS, 0);
ADCSequenceConfigure(ADC1_BASE, 0, ADC_TRIGGER_ALWAYS, 1);

ADCReferenceSet(ADC0_BASE,ADC_REF_EXT_3V);
ADCReferenceSet(ADC1_BASE,ADC_REF_EXT_3V);
ADCSequenceEnable(ADC0_BASE, 0);
ADCSequenceEnable(ADC1_BASE, 0);

uDMAEnable();
uDMAControlBaseSet(udmaCtrlTable);

uDMAChannelAssign(UDMA_CH24_ADC1_0);

ADCSequenceDMAEnable(ADC0_BASE,0);
ADCSequenceDMAEnable(ADC1_BASE,0);

// uDMAChannelAttributeDisable(UDMA_CHANNEL_ADC0, UDMA_ATTR_ALL);
// uDMAChannelAttributeDisable(UDMA_SEC_CHANNEL_ADC10, UDMA_ATTR_ALL);
// uDMAChannelAttributeEnable(UDMA_CHANNEL_ADC0, UDMA_ATTR_USEBURST);
// uDMAChannelAttributeEnable(UDMA_SEC_CHANNEL_ADC10, UDMA_ATTR_USEBURST);

uDMAChannelControlSet(UDMA_CHANNEL_ADC0 | UDMA_PRI_SELECT, UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_ARB_1);
uDMAChannelControlSet(UDMA_CHANNEL_ADC0 | UDMA_ALT_SELECT, UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_ARB_1);
uDMAChannelControlSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_PRI_SELECT, UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_ARB_1);
uDMAChannelControlSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_ALT_SELECT, UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_ARB_1);

uDMAChannelEnable(UDMA_CHANNEL_ADC0);
uDMAChannelEnable(UDMA_SEC_CHANNEL_ADC10);

uDMAChannelTransferSet(UDMA_CHANNEL_ADC0 | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG,(void *)(ADC0_BASE + ADC_O_SSFIFO0),g_ui32Src0ABuf, sizeof(g_ui32Src0ABuf));
uDMAChannelTransferSet(UDMA_CHANNEL_ADC0 | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG,(void *)(ADC0_BASE + ADC_O_SSFIFO0),g_ui32Src0BBuf, sizeof(g_ui32Src0BBuf));
uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG,(void *)(ADC1_BASE+ADC_O_SSFIFO0),g_ui32Src1ABuf, sizeof(g_ui32Src1ABuf));
uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG,(void *)(ADC1_BASE+ADC_O_SSFIFO0),g_ui32Src1BBuf, sizeof(g_ui32Src1BBuf));

uDMAChannelRequest(UDMA_CHANNEL_ADC0);
uDMAChannelRequest(UDMA_SEC_CHANNEL_ADC10);

ADCIntEnableEx(ADC0_BASE, ADC_INT_DMA_SS0);
ADCIntEnableEx(ADC1_BASE, ADC_INT_DMA_SS0);
ADCIntEnable(ADC0_BASE, 0);
ADCIntEnable(ADC1_BASE, 0);
IntEnable(INT_ADC0SS0);
IntEnable(INT_ADC1SS0);

IntEnable(INT_UDMA);

this will gives adc data but no properly at all time. is there any mistake in this??

i am trying many time but never get result properly 

Hello Prateek

First of all change the burst size to 8 to read the data from the sequencer in one shot, instead of arbitrating for every data.

When you mention that the adc data is not proper all the time, please explain how you are checking it. Are you providing a static input during testing?

I am reading data in debugging.

you mean to say UDMA_ARB_1 to UDMA_ARB_8

Hello Prateek

Yes, that is correct. Also when debugging such an issue make sure you have 2 things in place i.e. Stimulus and control

1. The input signal is not defined here as a static value or changing value. Always have a static value so that result is fixed
2. Instead of Always trigger which causes you to no longer have control over the conversion, use something like a processor or gpio trigger where you can control the trigger during debug.

Please have a look at the software files in appdrivers from TIDM-TM4C129POEAUDIO.

When using ADCClockConfigSet for ADC1 you are using PLL. Depending on which tivaWare version, there is an issue with divide by 8. If using TivaWare 2.1.2 or earlier this would result in 60MHz for ADC which will be out of spec.

Hi Amit,

1- if i can change Trigger to processor then this will be the depend on software not hardware and i need hardware trigger thats wht i am taking trigger_ALways.

2- i am using earlier version of tiwaware. there is any other change within this design. i can change trigger level to processor not always.

Hello Prateek

If your application is not working, then debug requires that the example code be broken down into simpler and more manageable blocks. I can only give suggestions on how to debug the same.

Hi Amit,

i also take your suggestion for our application. i am trying many things by which i can mostly completed my design but this part will not work properly.

just give a view on this
uDMAChannelControlSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_PRI_SELECT, UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_ARB_8);

in this source address will incremet or Destination address.

just give your view on this.

Hello Prateek

Since the source is ADC's FIFO register, it "must" not be incremented. The destination address can be incremented by 32 or 16 bits as 12 bit data is to be read. The Size of the transfer may also be 16 bits.