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RTOS/TM4C129XKCZAD: TM4C129X LCD controller with external SRAM

Peter Borenstein
Mastermind 8695 points
Part Number: TM4C129XKCZAD

Tool/software: TI-RTOS

In the datasheet, Figure 26-4 shows the structure of the color palette followed by the picture data. What is the format of this picture data?

How does data get from the EPI to the LCD input FIFO shown in figure 26-1?

Is the palette RAM depicted in this figure the same as the palette RAM in figure 26-4? Asked another way, is the palette RAM stored with the picture data continuously referenced or does it get copied?

I am interested in using the TM4C129X to drive a 800x480 color TFT LCD screen. I would like to use 4 bits per pixel. My plan is to use 2 Mbits of external SRAM. The SRAM has a parallel interface. It uses 18 address lines to output 8 bits at a time.

I picked this SRAM because it suits the EPI interface. 

How the EPI interacts with the LCD DMA is unclear. My understanding is the EPI is configured to "pretend" to be at address 0x1000.0000. The frame buffer LCDDMABAFB0 is set to this address. The following "imaginary" addresses translate to SRAM. For example, address 0x10000008 is actually address 0x0008 of the SRAM. I do not understand the format of the 4 bit values; hence the above questions. 

Section 26.3.2 encourages doubling my SRAM to allow a second frame buffer. The LCD controller would output from one buffer while I am free to update the other. My application does not have to update the screen quickly. Thoughts on this? How would the EPI balance reads with writes? The SRAM buss can only do one thing at a time. Can the EPI FIFOs handle this balancing act?

  • 0
    Mastermind 8695 points
    What does the NIBMODE bit of the raster control registers, LCDRASTRCTL, do?

    In table 26-5 , for the value X10, should be LCDAC be output enable instead of AC Bias?
  • 0
    TI__Guru 72500 points

    Peter Borenstein said:
    In the datasheet, Figure 26-4 shows the structure of the color palette followed by the picture data. What is the format of this picture data?

    If you are using 4 bits per pixel, the data represents each pixel. The first word (32-bits) describe the first 8 pixels. By default bits 3-0 identify the color of the first pixel by selecting its color from the color palette. The bit order can optionally be swapped (bits 31-28 represent the first pixel), and the location of the first pixel is determined by the rotation selected (normal means first pixel is top left and they increment from left to right).

    Peter Borenstein said:
    How does data get from the EPI to the LCD input FIFO shown in figure 26-1?

    The LCD controller has its own DMA that you configure to read from the EPI.

    Peter Borenstein said:
    Is the palette RAM depicted in this figure the same as the palette RAM in figure 26-4? Asked another way, is the palette RAM stored with the picture data continuously referenced or does it get copied?

    The color palette gets copied into the LCD controller. If the color palette does not change, you can just copy it once and then change the mode to only copy the data. See the PALMODE bits of LCDRASTRCTL register on page 1877 of the datasheet.

    You may have a problem with an 8-bit wide static RAM being too slow and causing a FIFO underflow. An SDRAM might be faster. The bux matrix arbitrates the LCD DMA reads and any CPU writes to the RAM. You just need to have enough bandwidth. You can synchronize updates to the display RAM between the DMA EOF (end of frame) and the Raster Mode Frame done signal. There are no LCD DMA reads during this time.

  • 0 in reply to Peter Borenstein
    TI__Guru 72500 points

    Peter Borenstein said:
    What does the NIBMODE bit of the raster control registers, LCDRASTRCTL, do?

    I honestly don't know and am not familiar with a case where it was used.

    Peter Borenstein said:
    In table 26-5 , for the value X10, should be LCDAC be output enable instead of AC Bias?

    Yes, in this mode that would be the proper description of its function.