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TMS570LS3137: SPI Loopback SelfTest

Arriy
Expert 1720 points
Part Number: TMS570LS3137


Hello.

I refer to SafetyManual(SPNU511D).

I want to implement "SPI1A:Boot Time Software Test of Function Using I/O Loopback".

To implemnent I have two questions.Please give me advice.

(1) Set the "IOLPBKSTENA" bit of the "I/O Loopback Test Control Register(IOLPBKTSTCR)" to Ah to enable the loop back test mode.

      After "CTRL DESYNC" bit is set to "1", inducing of the desync error.

      But "DESYNCFLG" bit of the "SPI Flag Register (SPIFLG)" is not set...

      Also "CTRL PARERR", "CTRL TIMEOUT", "CTRL DLENERR" too.

(2) I want to implement intentionally fault injection test to Overrun error.

     How to set the "RXOVRNINTFLG" bit of the "SPI Flag Register (SPIFLG)" ?

     Is it possible to intentionally inject fault ?

Best Regards

  • 0
    TI__Guru**** 199096 points
    Hello,

    Have you enable the interrupts for those errors? I will do a test to check.

    I don't think we can inject overrun error to SPI.

    Regards,
    QJ
  • 0 in reply to QJ Wang
    Expert 1720 points
    Hello QJ.
    Thank you for your support.

    > Have you enable the interrupts for those errors?
    I don't enable interrupts.
    Currently, the module of the communication partner is not implemented, and communication can not actually be received.

    If interrupts are not enabled, will RXOVRNINTFLG bit of the "SPI Flag Register (SPIFLG)"not be set?
    Does not an error occur if there is no other communication partner ?
    Is there a way to spuriously generate an error even if there is no partner ?

    Best Regards
  • 0 in reply to Arriy
    TI__Guru 59540 points
    Hello Arriy,

    You should be able to create the Overrun Error by sending 2 back to back messages while not reading the first message from the Receive buffer before the second message is received. Interrupts should not be required and you should be able to see the flag set in the error flag register. Note that the error flags are cleared by reading to be sure to capture the content in a RAM variable.
  • 0 in reply to Chuck Davenport
    Expert 1720 points

    Thank you for your answer.

    With reference to your opinion,after the sender is implemented, I will try to generate an overrun error.

    What I can do now, generate an error other than overun error.

    By using the register of "I/O-Loopback Test Control Register (IOLPBKTSTCR)",

    it was confirmed by CCS that 1 is set to the bit to be the target of error to be generated.

    But  error is not indicated at "SPI Flag Register (SPIFLG)"....

    Is there anything I have to be careful about doing this loopback test ?

    Is there anything more likely to be missed?

    Best Regards

  • 0 in reply to Arriy
    TI__Guru**** 199096 points

    Hello Arriy,

    I did a test of SPI IO loopback. I injected an error of data length, parity error, bit error, chip select, and got error flag set. I didn't get the flag for desyn error in my test, and will do more test.The breakpoint was added at while() before reading the SPIBUF.

    Here is my test code:

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Expert 1720 points

    Hello QJ.

    Thank you for your testing.

    I injected an error of data length, parity error, bit error, time out, desync,and didn't got error flag set.

    I got error flag is bit error only. I wonder why ?...

    Below is my souce code.Please give me anything advice.

    It is for debugging, calling "spiEnableLoopback" with "spiTransmitAndReceiveData".
    The processing of spiEnableLoopback will be explained later.

    Below function is "spiEnableLoopback " line 602 at above picture.

    This function is enable loopback and error.(In below picture is enable to data length error)

    "Loopbacktype" is set to digital.

    Best Regards

  • 0 in reply to Arriy
    Expert 1720 points
    Hello.
    Any update on this?

    Best Regards
    Arriy