TM4C1299NCZAD: EEPROM Endurance Description

Hi Pedro,
Hope this post will answer your question.
e2e.ti.com/.../1671100

Charles,

Let me corroborate:

• The EEPROM is described as 96 blocks of 16 words or 96 pages.
• 2-page is 32 contiguous words or 2 adjacent blocks which is the sector size
• Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion). This is writing to same address at all even blocks (word X of block0-block2-block4, etc.) or all even blocks (word X of block1-block3-block5, etc.)
• Endurance of 15M operations (when cycling through two pages ) per each 2-page block. This is writing 32 words at a time at word0-word31 of a block0, then word0-word31 of a block0 again and again. Similarly cycling through word0-word31 of a block1, or block2, block3, etc.,

Is this correct?

best regards,

  Pedro

Hi Pedro,

   One block consists of 2-pages in 32 contiguous words which is the sector size. 500k writes endurance means you can write to a fixed offset of either page 500K times. Let's say you write to wordX of page1 followed by write to wordY of page2 and repeat this operation 500k times. Note that there are two pages in one block which is equivalent to one sector. One sector is an unit for sector erase operation.  

  To get maximum 15M writes, it means that you will need to cycle through the two pages by first writing word0 followed by write to word1.... and continue to write word31 and you repeat this process you can get 15M operations. 

Charles,

Thanks for the info. Once a block wears out, how does the 32-bit word worn respond to access? Are neighboring cells affected?

What happens if we write to a memory cell, sporadically, but exceed 500K or 15M writes?

Best regards,
Pedro

Great insight Pedro - very well thought & presented probings.

Charles - might you advise if both (500K & 15M "operations") are determined by "theory/calculations" or via "real-world" life testing? If the former (theory) - has any attempt been made to verify w/real-world results?

Further - is it not true (or likely) that: system clock, MCU temperature, EEPROM access frequency, and MCU's "age" - individually and/or in total - impact results?

Hi Pedro, cb1,
Sorry, I'm not an expert in how the flash/EEprom is actually tested and qualified for a given technology so probably can't give a good answer from the standpoint of solid state physic. Each write/erase cycle degrades the bit cell and each bit can only sustain certain amount of degradation before it becomes unreliable, meaning it may still function but not consistently with margin. If a bit becomes unreliable, the logical word to which it belongs is unreliable for access. It does not change the behavior from a user point of view even the other 31 bits are 90% into their wearing level or 0%. All I can say is that if you exceed the specified number of writes you are on your own because you exceed TI's published limit.

For other MCUs that I had worked with before, the number of write/erase cycles were specified based on real test data across PVT (process, voltage, temperature) corner with enough margin. I can try to find out how the 15M cycles is obtained.

Thank you, Charles. Along w/"PVT" we may consider the impact of age - especially so when the device undergoes fairly rapid temperature changes/extremes. (surely (near) automotive use - but true as well for lesser environments - when the MCU transitions from "cold" (powered off) to full speed/current (power on) operation...)

Hi cb1,
Certainly the impact of aging is taken into account, not just for flash/EEprom but also for the device as a whole. HTOL is a type of stress test that is used to simulate the transistor aging. Semiconductor vendors may employ design margin to account for the effect of transistor aging (NBTI/CHC) and other factors (fab-to-fab transition, intra-die transistor variation, I/R drop, PLL jitter and etc) that can negatively impact the device performance.