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CCS/TM4C123GH6PGE: Memory over lap when I call GPIOIntRegister()

Part Number: TM4C123GH6PGE

Tool/software: Code Composer Studio

Dear Supporter

I'm coding 1 project, I have a problem, source code is show below:

/* PORTJ initial */
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
GPIOPinTypeGPIOInput(GPIO_PORTJ_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
GPIOIntEnable(GPIO_PORTJ_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
GPIOIntTypeSet(GPIO_PORTJ_BASE,GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3,GPIO_RISING_EDGE);
GPIOIntRegister(GPIO_PORTE_BASE, GPIOA_Interrupts_Handler);
/* Enable interrupts */
IntEnable(INT_GPIOJ);

When I Build it, the error: 

<Linking>
"../tm4c123gh6pge.cmd", line 41: error #10099-D: program will not fit into available memory. run placement with alignment fails for section ".vtable" size 0x26c , overlaps with ".vecs", size 0x360 (page 0)

When I comment GPIOIntRegister(GPIO_PORTE_BASE, GPIOA_Interrupts_Handler); -> build OK ( GPIOA_Interrupts_Handler() is defined )

I use bios_6_35_01_29, Code Composer Studio 6.2.0, xdctools_3_32_01_22_core, TivaWare_C_Series-2.1.3.156, tirtos_tivac_2_16_01_14

  • I can shed some light.  But I cannot explain everything.

    It is likely that, when you program does not call GPIOIntRegister, it fits in whatever memory range is used for the output section .vtable, but just barely.  When you add in that one additional function call, your program grows by a little bit more, and now it doesn't fit.  I presume GPIOIntRegister comes from some library.  When your program doesn't call it, it is not included in the link.  When your program calls it, the linker has to put one more function in .vtable, and runs out of space.  

    I cannot tell you the best way to fix this problem.  For that, this thread is moving to the TM4C devices forum.

    Thanks and regards,

    -George

  • the problem is:

    HWI create .vecs at 0x20000000

    file interrupts.c: #pragma DATA_SECTION(g_pfnRAMVectors, ".vecs")

    in *.cmd, auto gen .vtable in Section as 0x20000000

    Fix: goto *.cmd change name .vtable -> .vecs

    SECTIONS
    {
    .intvecs: > APP_BASE
    .text : > FLASH
    .const : > FLASH
    .cinit : > FLASH
    .pinit : > FLASH
    .init_array : > FLASH

    .vecs : > RAM_BASE     ( change here )
    .data : > SRAM
    .bss : > SRAM
    .sysmem : > SRAM
    .stack : > SRAM
    }

  • Hi,
    Glad your problem solved.