Other Parts Discussed in Thread: HALCOGEN
Tool/software: Code Composer Studio
Hello everyone. I'm developing a board based on Texas TMS570 MCU. I' Have a problem on SPI3 interface with 3 chip select pin, I'm not using multibufferd mode. On SPI3 I have connected 3 Analog Devices gyro P/N ADXRS453. I use SCLK, MISO, MOSI, SCS(0), SCS(1), SCS(2). I want to read each sensor independently.
To select a specific chip select pin before read a use:
dataconfig1_t.CSNR = SPI_CS_0;
or
dataconfig1_t.CSNR = SPI_CS_1;
or
dataconfig1_t.CSNR = SPI_CS_2;
But when I try to read a single sensor (ie the one on line SCS(1)), all 3 chip select will activate at same time!!! (all 3 cs go low!!). How to programmatically set a single chip select? I have set all 3 chip select as funcional in halcogen, do I have to set them as GPIO and than set cs manually?
void spiInit(void)
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
/** @b initialize @b SPI3 */
/** bring SPI out of reset */
spiREG3->GCR0 = 0U;
spiREG3->GCR0 = 1U;
/** SPI3 master mode and clock configuration */
spiREG3->GCR1 = (spiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */
| 1U); /* MASTER */
/** SPI3 enable pin configuration */
spiREG3->INT0 = (spiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */
/** - Delays */
spiREG3->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */
| (uint32)((uint32)0U << 16U) /* T2CDELAY */
| (uint32)((uint32)0U << 8U) /* T2EDELAY */
| (uint32)((uint32)0U << 0U); /* C2EDELAY */
/** - Data Format 0 */
spiREG3->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)0U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)89U << 8U) /* baudrate prescale */
| (uint32)((uint32)16U << 0U); /* data word length */
/** - Data Format 1 */
spiREG3->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)0U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)89U << 8U) /* baudrate prescale */
| (uint32)((uint32)16U << 0U); /* data word length */
/** - Data Format 2 */
spiREG3->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)0U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)89U << 8U) /* baudrate prescale */
| (uint32)((uint32)16U << 0U); /* data word length */
/** - Data Format 3 */
spiREG3->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)0U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)89U << 8U) /* baudrate prescale */
| (uint32)((uint32)16U << 0U); /* data word length */
/** - set interrupt levels */
spiREG3->LVL = (uint32)((uint32)0U << 9U) /* TXINT */
| (uint32)((uint32)0U << 8U) /* RXINT */
| (uint32)((uint32)0U << 6U) /* OVRNINT */
| (uint32)((uint32)0U << 4U) /* BITERR */
| (uint32)((uint32)0U << 3U) /* DESYNC */
| (uint32)((uint32)0U << 2U) /* PARERR */
| (uint32)((uint32)0U << 1U) /* TIMEOUT */
| (uint32)((uint32)0U << 0U); /* DLENERR */
/** - clear any pending interrupts */
spiREG3->FLG |= 0xFFFFU;
/** - enable interrupts */
spiREG3->INT0 = (spiREG3->INT0 & 0xFFFF0000U)
| (uint32)((uint32)0U << 9U) /* TXINT */
| (uint32)((uint32)0U << 8U) /* RXINT */
| (uint32)((uint32)0U << 6U) /* OVRNINT */
| (uint32)((uint32)0U << 4U) /* BITERR */
| (uint32)((uint32)0U << 3U) /* DESYNC */
| (uint32)((uint32)0U << 2U) /* PARERR */
| (uint32)((uint32)0U << 1U) /* TIMEOUT */
| (uint32)((uint32)0U << 0U); /* DLENERR */
/** @b initialize @b SPI3 @b Port */
/** - SPI3 Port output values */
spiREG3->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)0U << 3U) /* SCS[3] */
| (uint32)((uint32)0U << 4U) /* SCS[4] */
| (uint32)((uint32)0U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)0U << 9U) /* CLK */
| (uint32)((uint32)0U << 10U) /* SIMO */
| (uint32)((uint32)0U << 11U); /* SOMI */
/** - SPI3 Port direction */
spiREG3->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)1U << 3U) /* SCS[3] */
| (uint32)((uint32)1U << 4U) /* SCS[4] */
| (uint32)((uint32)1U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)1U << 9U) /* CLK */
| (uint32)((uint32)1U << 10U) /* SIMO */
| (uint32)((uint32)0U << 11U); /* SOMI */
/** - SPI3 Port open drain enable */
spiREG3->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */
| (uint32)((uint32)0U << 1U) /* SCS[1] */
| (uint32)((uint32)0U << 2U) /* SCS[2] */
| (uint32)((uint32)0U << 3U) /* SCS[3] */
| (uint32)((uint32)0U << 4U) /* SCS[4] */
| (uint32)((uint32)0U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)0U << 9U) /* CLK */
| (uint32)((uint32)0U << 10U) /* SIMO */
| (uint32)((uint32)0U << 11U); /* SOMI */
/** - SPI3 Port pullup / pulldown selection */
spiREG3->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)1U << 3U) /* SCS[3] */
| (uint32)((uint32)1U << 4U) /* SCS[4] */
| (uint32)((uint32)1U << 5U) /* SCS[5] */
| (uint32)((uint32)1U << 8U) /* ENA */
| (uint32)((uint32)1U << 9U) /* CLK */
| (uint32)((uint32)1U << 10U) /* SIMO */
| (uint32)((uint32)1U << 11U); /* SOMI */
/** - SPI3 Port pullup / pulldown enable*/
spiREG3->PC7 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)1U << 3U) /* SCS[3] */
| (uint32)((uint32)1U << 4U) /* SCS[4] */
| (uint32)((uint32)1U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)0U << 9U) /* CLK */
| (uint32)((uint32)0U << 10U) /* SIMO */
| (uint32)((uint32)0U << 11U); /* SOMI */
/* SPI3 set all pins to functional */
spiREG3->PC0 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)0U << 3U) /* SCS[3] */
| (uint32)((uint32)0U << 4U) /* SCS[4] */
| (uint32)((uint32)0U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)1U << 9U) /* CLK */
| (uint32)((uint32)1U << 10U) /* SIMO */
| (uint32)((uint32)1U << 11U); /* SOMI */
/** - Initialize TX and RX data buffer Status */
g_spiPacket_t[2U].tx_data_status = SPI_READY;
g_spiPacket_t[2U].rx_data_status = SPI_READY;
/** - Finally start SPI3 */
spiREG3->GCR1 = (spiREG3->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
/* USER CODE BEGIN (3) */
/* USER CODE END */
}
