TMS570LS3137: N2HET measurement capability

Scott, 

As many as there are HET pins.  The limitation is not on the # of signals;  it is on how fast the signals can change. 

Your high pulse width and low pulse width generally need to be at least a loop resolution clock long (both of them) but check the datasheet for this spec.

Also check the silicon errata for any variances.

Hello, and thanks for the response. I have a follow up question.

The TMS570LS31x Technical Reference Manual states in chapter 20 that only one instruction specifying a high resolution operation (hr_lr=HIGH) is allowed to execute per loop resolution period. But the other instructions can be used in standard resolution mode (bit set to 1).

Is this per each N2HET pin so that each pin could have one HR instruction in HR mode per loop? Or is it saying only one HR instruction in HR mode can be performed per loop regardless of how many pins are being captured?

Thanks,

Scott

There is a hardware 'timer' that is only 7 bits for each pin. 

When you execute an instruction in HR mode it configures that timer.  That is how the HET achieves high resolution measurements while sampling basically at loop resolution. 

So for example, the capture instruction is told when it executes whether there was an edge detected during the last loop;  but if it is executed in HR mode it will use that 7 bit hardware timer to determine the *offset* into the loop of the edge occurrance - and this is how you get the ~10ns resolution.

It's also where the restriction comes from of one HR instruction per loop - there is only one hardware timer per pin so that it can only perform one function at a time and respond only to one event per loop.   

There's a sort of 'workaround' on top of this - you can gang the hardware timers (HR Structures) from a pair of pins even&odd like 0,1  or 2,3  and make them operate on the even pin.   This is what the HRSHARE, ANDSHARE and XORSHARE modes are all about  (HRSHARE is for inputs,   AND/XOR are for outputs). 

But if you use this extension you still code the same way - one instruction per 'pin' per loop but when you operate on the odd pin # it actually is tied also to the even pin in the pair. 

Anyway, there is an HR structure for each pin and so you can execute one HR instruction per pin per loop. 

Hi Scott,

Yes those pins suffer from a silicon issue ..  

It's a long story but while they all have the hi-res structure there is a silicon bug which causes them to occasionally capture the lower 7 bits incorrectly.   

I think it's something like if the incoming edge lines up exactly at the loop resolution period then the lower 7 bits are corrupt;  they might read the lower 7 bits of the previous capture instead of what they should read for the current capture. 

So I think you're right - you should avoid using these pins. 

This is somewhat specific to the 31xx and 21xx series parts because it's a silicon bug but one that we don't have any design slots left to fix.

Best Regards,

Anthony

Hi Anthony,

Thanks for the response! I have another follow-up question:

So to confirm does that mean that, since no two adjacent odd and even pins for N2HET2 have YES in "SUPPORTS 32-BIT CAPTURE" column of datasheet table 7-13, that HR sharing function cannot be used for N2HET2? And that HR sharing can only be done on N2HET1?

Thanks again!

Scott

Hi Anthony,

I have a follow up question regarding HR sharing. The reference manual says that the odd HET pins that are configured for HR sharing can still be accessed as general inputs/outputs. But what about the other multiplexed functions associated with those odd pins? Can the multiplexed functions still be accessed as well? For example, if PGE package pins 118 and 6 are configured for HR sharing for N2HET1[10] and N2HET1[11], can the other multiplexed functions MIBSPI3NCS[4] or N2HET2[18] associated with pin 6 still be used? Or can pin 6 only be used as GPIO?

Thanks,

Scott