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TMS570LC4357: EMIF bus transaction when CEnCFG ASIZE=1 and requesting a 32-bit word

Kendall
Prodigy 60 points
Part Number: TMS570LC4357

In "SPNU563-May 2014" Section 21.2.6.3, Table 21-15, the following example is provided. "a request for a 32-bit word would require four external access when ASIZE=0".

1) Is this four separate bus transactions with EMIF_nCS[n] going high between each transaction?

2) Will a request for a 32-bit word require two external access when ASIZE=1?

3) Is there a timing diagram showing this behavior?

  • 0
    TI__Guru**** 196686 points
    Hi Kendal,

    An asynchronous request for 4 bytes will require four access cycles using an 8-bit data bus and only two access cycle using a 16-bit data bus. Since the read (or write) operation is directly proceeded by another read (or write) operation, no turn-around (TA) cycles are inserted (CS does not go to high). Please check the diagram in datasheet at page 110-111.

    Regards,
    QJ
  • 0 in reply to QJ Wang
    Prodigy 60 points

    The figures on "SPNS195C -FEBRUARY 2014-REVISED JUNE 2016" page 110-111 show one data transfer while EMIF_nCS[n] is low. Where in the data sheet or reference manual does it explain or show EMIF_nCS[n] staying low during a 4 byte request on a 16-bit data bus (ASIZE=1) and/or EMIF_nCS[n] staying low on an 8-bit data bus (ASIZE=0)?