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TMS570LS3137: Efuse SelfTest and ESM Error

Part Number: TMS570LS3137

Hello.

I have question at efuse error.

ESM error flag Group 1 Channel 40 is not set, I don't know why in this case.

Below code is "efcStuckZeroTest" in "sys.selftest.c".

In this function substitute "EFC_INSTRUCTION_INFO_EN" for "uint32 error_checks".

After, execute "efcREG->BOUNDARY = OUTPUT_ENABLE; " .

I think that these operations will set a single bit error to ESM Group 1 Channel 40.

*/
/* SourceId : SELFTEST_SourceId_012 */
/* DesignId : SELFTEST_DesignId_014 */
/* Requirements : HL_SR402 */
boolean efcStuckZeroTest(void)
{
/* USER CODE BEGIN (29) */
/* USER CODE END */

    uint32 ESM_ESTATUS4, ESM_ESTATUS1;

    boolean result = FALSE;
    uint32 error_checks = EFC_INSTRUCTION_INFO_EN  |
                                  EFC_INSTRUCTION_ERROR_EN |
                                  EFC_AUTOLOAD_ERROR_EN      |
                                  EFC_SELF_TEST_ERROR_EN   ;

    /* configure the output enable for auto load error , instruction info,
         instruction error, and self test error using boundary register
         and drive values one across all the errors */
    efcREG->BOUNDARY = ((uint32)OUTPUT_ENABLE | error_checks);

    /* Read from the pin register. This register holds the current values
         of above errors. This value should be 0x5c00.If not at least one of
         the above errors is stuck at 0. */
    if ((efcREG->PINS & 0x5C00U) == 0x5C00U)
    {
        ESM_ESTATUS4 = esmREG->SR4[0U];
        ESM_ESTATUS1 = esmREG->SR1[2U];
        /* check if the ESM group1 channel 41 is set and group3 channel 1 is set */
        if (((ESM_ESTATUS4 & 0x200U) == 0x200U) && ((ESM_ESTATUS1 & 0x2U) == 0x2U))
        {
           /* stuck-at-zero test passed */
           result = TRUE;
        }
    }

    /* put the pins back low */
    efcREG->BOUNDARY = OUTPUT_ENABLE;

    /* clear group1 flag */
    esmREG->SR4[0U] = 0x200U;

    /* clear group3 flag */
    esmREG->SR1[2U] = 0x2U;

    /* The nERROR pin will become inactive once the LTC counter expires */
    esmREG->EKR = 0x5U;

    return result;
}

Best Regards

  • Hello,

    You have to set the "Single Bit Error OE" which is bit 16 in EFCBOUND. Otherwise setting bit 20 only will not drive the single bit error and set the channel 40 of ESM error group 1.

    Regards,
    QJ
  • Hello QJ

    Thank you for your reply.

    Please refer to below operation,

    "efcREG->BOUNDARY = ((uint32)OUTPUT_ENABLE | error_checks);".

    "OUTPUT_ENABLE" is 0x0003C000.This is set to bit 16.

    In addition to bit 16, furthermore bits 14 to 21 are also set.

    Still there is no report to ESM Group 1 Channel 40.

    Best Regards