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TM4C1230E6PM: TM4C1230 SPI max speed in Master/Slave mode

Edward Chang
Intellectual 1630 points
Part Number: TM4C1230E6PM

Hi,

What are the max speed in SPI Master and Slave modes? Will they be different?

I saw this post, and it seems the max speed is 40MHz, right?

Regards,

Edward

  • 0
    TI__Guru**** 190806 points
    Hi Edward,
    This is what is shown in the datasheet.

    The frequency of the output clock SSInClk is defined by:
    SSInClk = SysClk / (CPSDVSR * (1 + SCR))
    Note: The System Clock or the PIOSC can be used as the source for the SSInClk. When the
    CS field in the SSI Clock Configuration (SSICC) register is configured to 0x5, PIOSC is
    selected as the source. For master mode, the system clock or the PIOSC must be at least
    two times faster than the SSInClk, with the restriction that SSInClk cannot be faster than
    25 MHz. For slave mode, the system clock or the PIOSC must be at least 12 times faster
    than the SSInClk, with the restriction that SSInClk cannot be faster than 6.67 MHz.
  • 0 in reply to Charles Tsai
    TI__Intellectual 1630 points
    So if I need a MCU that can receive SPI data at 25MHz in Slave mode. Do you have any recommendation? TM4C129 series?
  • 0 in reply to Edward Chang
    TI__Guru**** 190806 points
    Hi Edward,
    This is from the TM4C129 datasheet. So 25Mhz for slave mode is not possible.

    The frequency of the output clock SSInClk is defined by:
    SSInClk = SysClk / (CPSDVSR * (1 + SCR))
    Note: SYSCLK or ALTCLK is used as the source for the SSInClk depending on how the CS field
    in the SSI Clock Configuration (SSICC) register is configured. For master legacy mode,
    the SYSCLK or ALTCLK must be at least two times faster than the SSInClk, with the
    restriction that SSInClk cannot be faster than 60 MHz. For slave mode, SYSCLK or ALTCLK
    must be at least 12 times faster than the SSInClk. In slave legacy mode, the maximum
    frequency of SSInClk is 10 MHz.