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EK-TM4c1294xl: PWM dead band delay ends up as an unintended delay pulse in trapezoidal wave form

Genatco
Guru 55913 points
Part Number: EK-TM4C1294XL
Other Parts Discussed in Thread: TM4C1294NCPDT

PWM0 Configuration: 

PWM0 Up/Down count, dead band GEN local update, GEN sync, GEN sync global updates. PWM output update mode is set as sync local.

Conditions steps of PWM0 output call:

1. Cyclic enabling or disabling dead band delay register via PWMDBnCTRL for PWM0 specific test criteria. 2. Turn off all previous PWM output pins. 3. Assert a binary code change to PWMENABLE output register.

 Issue:

The PWM output on GPIO pins delay period ends up as an unintended pulse period being posted after a new binary code and trapezoidal pulse is output on low side of inverter, versus an delay being appended to a new pulse. However the pulse output PWM-A (high side) of any generator seems to have the required delay period appended to the new output pulse but PWM0 generators may not be dropping PWM-B until after the pulse is output or something like that is occurring.

TM4C1294NCPDT data sheet states:
If the dead-band generator is enabled, the pwmB signal is lost and two PWM signals are generated based on the pwmA signal. The first output PWM signal, pwmA' is the pwmA signal with the rising edge delayed by a programmable amount. The second output PWM signal, pwmB', is the inversion of the pwmA signal with a programmable delay added between the falling edge of the pwmA signal and the rising edge of the pwmB' signal. 

Question is should SW be made to return after enabling the dead band generators, now existing in step 1 in the call used to change binary code, step 3 above? Are dead band generators automatically updated but only after each local GEN count zero and that is not exactly synchronous to PWM0 Output mode sync local when step 3 is occurring after PWMnDBCTRL enable bits are set or cleared in step 1? 

What is best method to enable and clear dead bands on 3 generators prior to cyclic binary code changes to PWMENABLE register output?  Should the dead band PWMnDBCTRL enable bit handling be a post operative update only after the binary code change step 3? Who's on first to catch any shoot through balls or does it even matter in the first few and very low duty cycles of PWM motor control? 

  • 0
    Guru 55913 points

    First of all I was somewhat wrong about the delay being appended and recalling the FET gate acting that way. However this is seemingly an easier issue of high side FET fast current decay causing low side PWM pulses to be present and spike far below ground and have a period of PWMnDBRISE/FALL registers values combined (160ns x 2).

    Low side PWM pulses (red oval) occur when minimum pulse width is more than 600ns wide and become small amplitude tick marks crossing zero when minimum pulse width is set below 800ns or less (slow FET current decay). The question then becomes why the fast decay low side pulse (red oval) is assuming the PWMnDBRISE/FALL as the minimum pulse width (320ns) when the RISE/FALL register value is 160ns?

  • 0 in reply to Genatco
    Guru 55913 points

    ONSemi specialists suggest to speed up the high side FETs to minimize switch node noise of inverter in slow current decay. It seems that may be accomplished by minimizing the FET off time or adjust the minimum pulse width as I did. But....

    Reducing the pulse width below 100ns also causes the low side FET off time to shorten near SOA warnings, in order to redirect inductive snub forward current to ground via FET junction and the body diode working in tandem. The alternative to heating the low side junction to dangerous levels might suggest statically reducing high side (PWM-A) FET decay time in the pulse width update process. The inverter is already out of symmetrical balance in slow current decay where the low side FET's duty cycle nears 100% and current recirculates in the high side of the inverter.

    The question still remains as to what is causing low side pulses to reflect the value of PWMnDBRISE/FALL register (PWM-B)??

    The low side PWM pulses are reduced or removed entirely by setting a minimum pulse width below 600ns (slow decay). Doing that also sets the minimum pulse width of PWM-A when PWMnDBCTRL is not enabled (cleared) for the FET turn on event of high side MOS. It seems the PWM-A/B dead band counters are not being released back to pass through mode if that is not first done every cycle.

    Please see https://community.fairchildsemi.com/thread/1032

  • 0 in reply to Genatco
    Guru 55913 points

    BP101 said:
    The question still remains as to what is causing low side pulses to reflect the value of PWMnDBRISE/FALL register (PWM-B)??

    PWM dead band counters PWMnDBCTRL enable bits are not disabling fast enough at updates if wider pulse widths of PWMB and Fixed delay periods PWMB bleed into PWMENABLE register and MCU output pins as a result of slow decay.

    Other words it is not practical to allow low side PWM in slow current decay of high side MOSFETS since it causes to much PWM ground noise and LMI engineers claim of low side PWM does not seem realistic in fast decay either. That is to say the architecture LMI released in an RDK has major issues with suppressing low side PWM noise. The RDK user manual stated it was possible to enable fast decay but it did not actually ever produce low side PWM. Also the TM4C1294 even being capable to produce equal sized PWM pulse widths PWMA/B presence of dead band delay seems to be a train wreck of sorts when fast decay mode is enabled after FOC slow decay mode is forced on.

    We developed a WA to fix that FOC motor startup transition of slow decay into fast decay mode but it seems the low side PWM results from dead band delay pulses and not pwmB output as expected. That seems to indicate dead band pwmB is not actually decoupling long enough from pwmA when PWMnDBCTRL enable bit is cleared in each PWMENABLE call cycle in order to produce a full sized pulse on pwmB.

    Undisclosed timing limitations might exist in the dead band counters.