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TM4C1294NCPDT: SPI MOSI level is incorrect

Edward Chang
Intellectual 1630 points
Part Number: TM4C1294NCPDT


Hi,

I would like to set TM4C1294 device to output SPI signal at 25MHz.

1. The level of MOSI is incorrect. Why? Is it required to add pullup resistor?

2. I was trying to set the SPI clock to 25MHz but the actual SPI clock will be 30MHz. If I set it to 20MHz, it will output 20MHz clock. It is weird when clock is over 20MHz.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/hello.7z

3. Is it possible to set either MISO or MOSI as open-drain? MISO and MOSI may be used at different voltage level.

Regards,

Edward

  • 0
    TI__Guru**** 191906 points

    Hi Edward,

      Did you observe the PA4 or the PA5 pin? PA4 is the TX pin in Legacy SSI mode and PA5 is the RX pin. I'm able to see TX pin on PA4 on the scope. 

      The SYSCLK is 120MHz. To get 25MHz you will need a fractional prescaler which is not supported. You can get closest to 30MHz with a divider of 4. 

  • 0 in reply to Charles Tsai
    TI__Intellectual 1630 points

    Hi Charles,

    I can see the signal from PA4. I still have two questions:

    1. Is it possible to set either MISO or MOSI as open-drain? MISO and MOSI may be used at different voltage level.

    2. If I would like to get 25MHz SSI clock, I need to set SYSCLK to 100MHz, right? I follow the step as the link, but it seem not working.

        2626.sysctl.c

    systick.h

    Regards,

    Edward

  • 0 in reply to Edward Chang
    Guru 117855 points

    Edward Chang said:
    ...would like to get 25MHz SSI clock, I need to set SYSCLK to 100MHz, right?

    Logically that's correct as 25MHz results from an integral divide of 100MHz.    That said - w/your MCU PLL (only) able to run at 320 or 480MHz - how do you propose an integral divide to yield 100MHz?"   While I don't use your MCU - I believe that's your, "gotcha."    (in a recent post here I listed the "usual suspect" System Clocks which (then) resulted from the "most usual" integral divisors.)   (100MHz was NOT among them!)

  • 0 in reply to cb1_mobile
    TI__Guru**** 191906 points
    Thanks cb1 for explaining the limitation on the SYSCLK.

    Edward, the SYSCLK = Fvco / (PSYSDIV + 1). With Fvco equal to either 480MHz or 320MHz you can't divide down to 100MHz. If you must have 25MHz then you may consider using the 25MHz MOSC as your source for SYSCLK. Or with SYSCLK=120MHz you can divide down the SSICLK to 24MHz. Can you do with 24MHz?

    The QSSI module cannot do open drain for SIMO and SOMI pins.
  • 0 in reply to Charles Tsai
    Guru 117855 points

    Note too that the QSSI module cannot support open drain of, "MISO or MOSI" as well...