TM4C1290NCPDT: TIVA crashes during ESD test

Firm/I have noted similar effect upon (another's) ARM Cortex M4 MCU - interesting (maybe telling) it too drives a TFT Display.

Our application was pseudo-military - thus stress/confidence testing was likely to be more severe than yours.    We persisted - probed, prayed - and may have gotten lucky.   (Our ESD issue resolved!)

May I suggest that you follow this procedure - which worked for us?

• We know your system is of - at least - "2 board complexity."   (MCU board & display)    Always we design/program our MCU boards so that they can be (reasonably) test/verified BY THEMSELVES.   We've found that "Off MCU board "cables/connections" often "invite" unwanted, destructive inputs.   I ask that you repeat your testing - but only after you (temporarily) BREAK the connection between LCD & MCU board.   (the objective is to determine "if" the MCU board - by itself - can survive hostile signal introduction.)
• Our design involved four pcbs - 3 "slaved" to the main MCU board - 2 of them (also) w/ARM MCUs.   (M0s)    Each/every board should be (similarly) isolated - and tested.   You are searching for (that/those) board(s) most susceptible to the hostile signal.   (in your case - we know of (just) 2 boards.)
• Vendor's Bob suggested that you, "measure VDD - but (only) after the system upset."    We found it more advantageous to design a, "Bulletproof/Faraday Shield protected"  monitor/logger which enjoyed the capability to capture & store live measurements!  (especially peaks)   Such a device or method hugely improves/speeds diagnostic capability.   [detail below - for those interested.] 
• Monitoring ALL other power supplies - critical circuits - also proves useful.   Our battery powered, monitor/logger, is small enough that several may be placed w/in an enclosure.

Findings:

• The TFT's back-light, (rather crude) switching supply proved (most) susceptible to the ESD gun - and served to "feed back" to our MCU board.
• Beefing up that supply - adding filtering & shielding - and minimizing inter-connection length - in combination - (almost) totally cured our issue.
• Several of our "Non-Main MCU boards" employed high-gain Instrumentation Amps - these were impacted.   The combination of shielded cable and RFI filters (right at the In-Amp's input pins) - again in combination - "quieted" these sub-boards.
• While adding cost - you may consider, "Conductive Spray Paint" covering the entirety of the inside of your enclosure's housing.   This provides a twin benefit - reducing the level of your RFI/EMD emissions & - if marketing claims are believed - absorbing (some) of your ESD level.
• Surprisingly (or not) sometimes simply "re-locating" boards has sizable impact upon board "discomfort" while "stressed.
• Insure that the "levels" of your ESD Gun are well noted during testing - and that the equipment has been recently calibrated - and that the ESD discharges occur w/consistent levels & target location. 
• [edit/added] note that - although adding complexity - the ESD test should be performed at/around the "normal" operating temperature of the "DUT."   However - if a reasonable amount of operation occurs "outside that norm" - then testing should expand to include those temperature conditions - to provide fullest confidence.

Performing EVERYTHING herein listed is (usually) NOT required.   Thoughtful & systematic testing (pre-commissioning) can identify the MAJOR trouble spots - those should be attacked first.

Note that it proves ALWAYS WISE to keep in quarantine your "base" completely unprotected unit - and those modified w/different levels of protection.   Both components, software & client demands may all impact the effectiveness of these techniques - you WILL require eased access to your "base protected units" (down-stream) so that you can efficiently compare/contrast against future builds (or returned field units).

[Monitor/logger detail]   

Rapid/clamping Power FETs  - protect the monitor/logger from excess (±)voltage.   Freed from the unwanted "disturbance & Antenna-like, pick-up" introduced (most always) by a scope probe - we collect high accuracy voltage data - ALONG w/the "PEAK-DETECTED Voltage" (both positive & negative!) - triggered by the ESD gun.   This (protected) monitor/logger provides the insight of a scope - but avoids its bulk & "unwanted signal introductions!"   Vitally - operation of such ESD guns w/scope connected - may introduce voltage transients IN EXCESS of the scope's input protection circuits!   (Lesson Learned: "Quick/easy/known/available" methods may (not always) prove best...(or survive the process!))

Bruno - thanks - appreciated.    (was trapped waiting for connecting flight) & "no one interesting" (but for moi) was at airport bar...)

I'm not so sure that "systematic" trumps:

• Sweat the details
• Assume nothing (at least little)
• How can the best possible - least impacting - measurements be obtained?   (even if - and especially if - No such capability exists - thus must be creatively designed & implemented!)
• Document everything
• One can never be: "too thin, too rich, or pay too much, "Attention to Detail."

Wise to note that the above should be executed (prior to) visiting the bar...

Really Tank's cb1 for your help and congratulations for your professionality.
I really appreciated it.
Our EUT is actually made up of five cards.
The CPU acts as "intelligent motherboard" with slots for :
- power supply board;
- TFT board;
- coprocessor board measurement;
- communication card (in this case a simple isolated RS485);

In Italy it is morning and we're starting to work now.
I will try to disconnect the daughter cards to identify the victim and will execute the recommended measurements.
Thank you all and I will keep you informed.
Michele