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TMS470MF0660x RST_ and PORRST_ timing

Hiroshi Kimizuka
Expert 4400 points
I have some questions about RST_ and PORRST_timing in page 36/37 of the TMS470MF0660x DataSheet(SPNS157).
 
1) In Table 5-1, the note (1) refers to PORRST_ input.  Is this also applicable to the input on RST_ pin ?
2) Is there any requirement to specify the setup time of VCCIOR>VCCIOPORH before VCC>VCCPORH ?
3) If the above #2 spec is not needed, is the low width of  PORRST_ upon power-on required as tsu(PORRST)r + tsu(VCCIOR)r + max(th(PORRST)r, th(PORRST)rio) = 1ms ?
4) Is the reset circuit upon Power-on-reset composed of the asynchronous registers ?   
5) In Table 5-2, the parameter tv(RST) looks as the output characteristic at the RST_ pin, since this is specified as "valid" timing. 
    If so, why does the RST_ signal become active after the PORRST_ had turned to inactive ?
6) What is the exact meaning of the second parameter of tv(RST);"Valid time, RST_ active (all others) ?
7) In Table 5-2, if the RST_ is considered as input signal, the tv(RST) should be as a hold time after PORRST inactive; th(RSTL-PORRSTH) ?        
8) Even in input mode, what is the exact meaning of the second parameter ?
9) Is there recommended condition of the low width(X*tc(OSC)) of the RST_ input to be asserted ?
10) In Table5-3, why is the parameter tv(PORRST)L specified as "valid time" though it is an input ?
    This should be a "hold time" as Table 5-1 specifies. 
Thank and Best Regards,
KIMIZUKA
  • 0
    TI__Guru 59540 points

    Q1) The note is applicable as indicated in the datasheet. Traditionally, nRST is an output; but, as you have indicated, it can also serve as an input in the case of a "soft" reset. I would suspect that the behavior of nRST with respect to the Vih and Vil parametrics would be similar but I do not have specific hardware or simulation data to support this suspicion.

    Q2) Alhough it is possible to use the device with the internal Vreg disabled, this is predominantly intended for testing the device and not for regular application use. So, in short, no. The only supply provided externally is Vccior;, thus, there is no need to specify the timing of Vcc with respect to Vccior.

    Q3) There is a glitch filter on the nPORRST pin. The requirement is that nPORRST be asserted for a time greater than the maximum filtered glitch for it to be recognized as an nPORRST assertion. See the spec parameter tf(nPORRST) in table 5.1 of the device datasheet. In the case of TMS470MF066x device family this max thershold for glitch filtering is 150ns.

    Q4) I am not certain what is being asked for here. There are many components that are dependent on nPORRST and many that are independent of nPORRST.While nPORRST is held, there are many registers and components within the device that are reset asynchronously of nPORRST

    Q5) As discussed, the primary intent of the nRST pin is to signal the outside system that a reset is ocurring/has ocurred on the device. In the case of a power on reset (nPORRST), the device takes 1024 cycles for OSC to become valid and propagate after nPORRST is released (inactive). Once this time passes, nRST will transition to inactive as well (indicating the device is fully out of reset). During this time that nRST has not propagated it is active.

    Q6) In the case of "all others" this means cases other than nPORRST. i.e., there are many scenarios internal to the device that can result in an internal reset. In these cases this parameter applies. It takes 8 cycles for the reset to propagate to the nRST pin.

    Q7) nRST is predominently used as an output to indicate to an external system that a reset has occurred. It also functions as an input in the case of a "soft" reset. Note that during a "soft" reset, the enire device is not reset. Indiviual features/functions within the device are idenified throughout the device documentation as being affected or not being affected by nRST. To guarantee a known starting point and full reset nPORRST should be used to reset the device.

    Q8) The input pulse width is as discussed in item 9 below. i.e., we do not specify a hold time for nRST other than the specified glitch filtering.

    Q9) The pulse width of nRST that is recognized as an assertion of nRST is not dependent on tc(OSC). This pin has a glitch filter implemented and any pulse must exceed this filtered with in order to be recognized as an assertion. this time is specified in table 5.1 as tf(RST) and indicates the pulse width must be greater than 150ns. 

     

    Q10) I think the statement on terminology is probably correct. A more important observation is that we have it specified in 2 locations which should probably be rectified before issuing the release of the final datasheet. What this is attempting to convey is that nPORRST must be held for 1ms AFTER Vccior reaches 3.0V.

     

  • 0 in reply to Chuck Davenport
    TI__Expert 4400 points

     

    Q1) In case of the configuration for nRST input, those characterization must be required.

    Q2) Since the No.5(tsu(VCCIOR)r) in Table 5-1 is specified, I think  the setup time of VCCIOR>VCCIOPORH before VCC>VCCPORH can also be specified as a symetrical fashion.    If the Vreg is applied, the No.5 parameter is also useless.

    Q3) If the tf(PORRST) is the only required specification, what is the meaning of the No.8 th(PORRST)rio parameter ?

            Can we ignore this No.8 ?

    Q4) Since there is no relative spec from ECLK, I just imagined there must be asynchronous FF for commonly used for sleep and normal.

    Q5) OK. I made misunderstanding of this parameter. Now I understand the nRST output can be active after the nPORRST becomes inactive high, and this makes the delay time which is specified as tv(RST) "valid" time.

    Q6) This means that many scenarios except nPORRST result in internal reset makes 8 cycles delay of nRST valid at the minimum.

    Q7) in case of the input configuration on nRST, the tf(RST) is the only required parameter in any scenario ?

    Q8) OK.

    Q9) If the low pulse width of RST input is not depending on tc(OSC),  this is because of secure the delay of the glitch filter rather than unavailable standard signal.

     Q10) You explained the nPORRST must be held for 1ms at minimum.  This means hold time, anyway.

    Thanks and Best Regards,