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TMS570LS3137: nPORRST setup time

Priya Kakarla Naga Lakshmi
Prodigy 130 points
Part Number: TMS570LS3137

Hi All,

The processor datasheet specifies a setup time requirement for nPORRST signal. This says that a minimum of 2µs setup time is to be provided before Vcc (1V2 line) goes below Vccporh (1.14V min) during power down.

The timing diagram taken from the datasheet is below. Please check parameter "7". Essentially, from the time under voltage on 1V2 line is detected to 1V2 going to 1.14V there should be a delay of at least 2µs. Could somebody help me with how this can be achieved? And what are the implications of not meeting this particular requirement? 

  • 0
    TI__Guru 59540 points
    Hello Priya,

    The danger of not honoring this specification for power down is indeterminate behavior of the MCU. i.e., if the core voltage drops below the specified voltage it's behaviour cannot be guaranteed. As such you may see, for examples, peripherals that misbehave and send unintended messages or IO toggling that is unintended. The potential for this 'misbehavior' is not limited to the examples provided and could even cause Flash corruptions orpermanent failures.

    One suggestion is to put sufficient capacitance on your 1.2V supply so that the ramp down of the core supply is sufficiently slow enough to allow this spec to be met. Another, more realistic, possibility is to use an external voltage supervisor to assert nPORRST or nRST once voltage drops below 1.14V. In some cases, there may even be a power good signal on your LDO or voltage regulator that can perform this function. To guarantee the spec is met you could even target a slightly higher voltage than 1.14V.