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RTOS: Initializing External RAM interface using GPIO functions before to C Runtime initialization

Other Parts Discussed in Thread: TM4C1294NCPDT

Tool/software: TI-RTOS

In  a  TM4C1294NCPDT microcontroller + TI-RTOS  enviroment  , in  order to enable an external memory before the C runtime   initialization,  we  are using  a   "reset function" as below  in .cfg:

 

var Startup = xdc.useModule('xdc.runtime.Startup');

var Reset = xdc.useModule("xdc.runtime.Reset");
Reset.fxns[Reset.fxns.length++] = "&sdram_init";

That works fine.  The problem  occurs  when     sdram_init  function  calls  the  GPIO functions such as  "SysCtlPeripheralEnable", " GPIOPinConfigure"   etc ,  it generates an exception  that halt  the program.

void sdram_init(void)
{

   SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);									/**< habilita EPI0	0xf0001000 */


    GPIOPinConfigure(GPIO_PH0_EPI0S0);											/**<  29| PH0|EPI0S0 				*/
    GPIOPinConfigure(GPIO_PH1_EPI0S1);											/**<  30| PH1|EPI0S1				*/
    GPIOPinConfigure(GPIO_PH2_EPI0S2);											/**<  31| PH2|EPI0S2				*/
    GPIOPinConfigure(GPIO_PH3_EPI0S3);											/**<  32| PH3|EPI0S3				*/
    GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS);							/**< inicializa porta H como EPI	*/

    GPIOPinConfigure(GPIO_PC7_EPI0S4);											/**< 22 | PC7 | EPI0S4 */
    GPIOPinConfigure(GPIO_PC6_EPI0S5);											/**< 23 | PC6 | EPI0S5 */
    GPIOPinConfigure(GPIO_PC5_EPI0S6);											/**< 24 | PC5 | EPI0S6 */
    GPIOPinConfigure(GPIO_PC4_EPI0S7);											/**< 25 | PC4 | EPI0S7 */
    GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);							/**< inicializa porta C como EPI	*/

    GPIOPinConfigure(GPIO_PA6_EPI0S8);											/**< 40 | PA6 | EPI0S8 */
   GPIOPinConfigure(GPIO_PA7_EPI0S9);											/**< 41 | PA7 | EPI0S9 */
    GPIOPinTypeEPI(GPIO_PORTA_BASE, EPI_PORTA_PINS);							/**< inicializa porta A como EPI	*/

    GPIOPinConfigure(GPIO_PG1_EPI0S10);											/**< 50 | PG1 | EPI0S10 */
    GPIOPinConfigure(GPIO_PG0_EPI0S11);											/**< 49 | PG0 | EPI0S11 */
    GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);							/**< inicializa porta G como EPI	*/

    GPIOPinConfigure(GPIO_PM3_EPI0S12);											/**< 75 | PM3 | EPI0S12 */
    GPIOPinConfigure(GPIO_PM2_EPI0S13);											/**< 76 | PM2 | EPI0S13 */
    GPIOPinConfigure(GPIO_PM1_EPI0S14);											/**< 77 | PM1 | EPI0S14 */
    GPIOPinConfigure(GPIO_PM0_EPI0S15);											/**< 78 | PM0 | EPI0S15 */
   GPIOPinTypeEPI(GPIO_PORTM_BASE, EPI_PORTM_PINS);							/**< inicializa porta M como EPI	*/

    GPIOPinConfigure(GPIO_PL0_EPI0S16);											/**< 81 | PL0 | EPI0S16 */
    GPIOPinConfigure(GPIO_PL1_EPI0S17);											/**< 82 | PL1 | EPI0S17 */
    GPIOPinConfigure(GPIO_PL2_EPI0S18);											/**< 83 | PL2 | EPI0S18 */
    GPIOPinConfigure(GPIO_PL3_EPI0S19);											/**< 84 | PL3 | EPI0S19 */
    GPIOPinTypeEPI(GPIO_PORTL_BASE, EPI_PORTL_PINS);							/**< inicializa porta L como EPI	*/

    GPIOPinConfigure(GPIO_PB3_EPI0S28);											/**< 92 | PB3 | EPI0S28 */
    GPIOPinTypeEPI(GPIO_PORTB_BASE, EPI_PORTB_PINS);							/**< inicializa porta B como EPI	*/

    GPIOPinConfigure(GPIO_PN2_EPI0S29);											/**< 109 | PN2 | EPI0S29 */
    GPIOPinConfigure(GPIO_PN3_EPI0S30);											/**< 110 | PN3 | EPI0S30 */
    GPIOPinTypeEPI(GPIO_PORTN_BASE, EPI_PORTN_PINS);							/**< inicializa porta N como EPI	*/

    GPIOPinConfigure(GPIO_PK5_EPI0S31);											/**< 62 | PK5 | EPI0S31 */
    GPIOPinTypeEPI(GPIO_PORTK_BASE, EPI_PORTK_PINS);							/**< inicializa porta K como EPI	*/

    EPIDividerSet(EPI0_BASE, 1);												/**< configura base de clock de  EPI	*/

    EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);										/**< configura EPI como SDRAM		*/

    EPIConfigSDRAMSet(EPI0_BASE, ( EPI_SDRAM_CORE_FREQ_50_100 |
			EPI_SDRAM_FULL_POWER |  EPI_SDRAM_SIZE_64MBIT), 468);				/**< configura clock 				*/

   EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_256MB | EPI_ADDR_RAM_BASE_6);	/**< configura tamanho máximo da sdram	*/

   while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ){_nop();}			/**< aguarda status de configuração dos registradores */


}

That sequence of  initialization   works  well  when  sdram_init is called directly from main,  but we need to do that before C Runtime  initialization  for use it for static variables. with apropriate linker settings

I ask   if  these   "GPIO" functions  can not be called before C Runtime  initialization   ?


Is there an  alternative method to initializing the pins to enable external  memory before  C Runtime initialization .

 

 

 

  • Can you use the Startup.firstFxns instead? These functions are called a little later in the boot process.

    Todd
  • The    function for ram  setup   was wrong , it lacked  "SysCtlPeripheralEnable" calls

    Now,  it works   as  an   "user reset function"

    So  the GPIO funtions can be used  before main().

    void sdram_init(void)
    {

    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOR);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOS);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOT);

    SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0); /**< habilita EPI0 0xf0001000 */

    //GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS); /**< inicializa porta H como EPI */

    GPIOPinConfigure(GPIO_PH0_EPI0S0); /**< 29| PH0|EPI0S0 */
    GPIOPinConfigure(GPIO_PH1_EPI0S1); /**< 30| PH1|EPI0S1 */
    GPIOPinConfigure(GPIO_PH2_EPI0S2); /**< 31| PH2|EPI0S2 */
    GPIOPinConfigure(GPIO_PH3_EPI0S3); /**< 32| PH3|EPI0S3 */

    GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS); /**< inicializa porta H como EPI */

    GPIOPinConfigure(GPIO_PC7_EPI0S4); /**< 22 | PC7 | EPI0S4 */
    GPIOPinConfigure(GPIO_PC6_EPI0S5); /**< 23 | PC6 | EPI0S5 */
    GPIOPinConfigure(GPIO_PC5_EPI0S6); /**< 24 | PC5 | EPI0S6 */
    GPIOPinConfigure(GPIO_PC4_EPI0S7); /**< 25 | PC4 | EPI0S7 */
    GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS); /**< inicializa porta C como EPI */


    GPIOPinConfigure(GPIO_PA6_EPI0S8); /**< 40 | PA6 | EPI0S8 */
    GPIOPinConfigure(GPIO_PA7_EPI0S9); /**< 41 | PA7 | EPI0S9 */
    GPIOPinTypeEPI(GPIO_PORTA_BASE, EPI_PORTA_PINS); /**< inicializa porta A como EPI */

    GPIOPinConfigure(GPIO_PG1_EPI0S10); /**< 50 | PG1 | EPI0S10 */
    GPIOPinConfigure(GPIO_PG0_EPI0S11); /**< 49 | PG0 | EPI0S11 */
    GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS); /**< inicializa porta G como EPI */

    GPIOPinConfigure(GPIO_PM3_EPI0S12); /**< 75 | PM3 | EPI0S12 */
    GPIOPinConfigure(GPIO_PM2_EPI0S13); /**< 76 | PM2 | EPI0S13 */
    GPIOPinConfigure(GPIO_PM1_EPI0S14); /**< 77 | PM1 | EPI0S14 */
    GPIOPinConfigure(GPIO_PM0_EPI0S15); /**< 78 | PM0 | EPI0S15 */
    GPIOPinTypeEPI(GPIO_PORTM_BASE, EPI_PORTM_PINS); /**< inicializa porta M como EPI */

    GPIOPinConfigure(GPIO_PL0_EPI0S16); /**< 81 | PL0 | EPI0S16 */
    GPIOPinConfigure(GPIO_PL1_EPI0S17); /**< 82 | PL1 | EPI0S17 */
    GPIOPinConfigure(GPIO_PL2_EPI0S18); /**< 83 | PL2 | EPI0S18 */
    GPIOPinConfigure(GPIO_PL3_EPI0S19); /**< 84 | PL3 | EPI0S19 */
    GPIOPinTypeEPI(GPIO_PORTL_BASE, EPI_PORTL_PINS); /**< inicializa porta L como EPI */

    GPIOPinConfigure(GPIO_PB3_EPI0S28); /**< 92 | PB3 | EPI0S28 */
    GPIOPinTypeEPI(GPIO_PORTB_BASE, EPI_PORTB_PINS); /**< inicializa porta B como EPI */

    GPIOPinConfigure(GPIO_PN2_EPI0S29); /**< 109 | PN2 | EPI0S29 */
    GPIOPinConfigure(GPIO_PN3_EPI0S30); /**< 110 | PN3 | EPI0S30 */
    GPIOPinTypeEPI(GPIO_PORTN_BASE, EPI_PORTN_PINS); /**< inicializa porta N como EPI */

    GPIOPinConfigure(GPIO_PK5_EPI0S31); /**< 62 | PK5 | EPI0S31 */
    GPIOPinTypeEPI(GPIO_PORTK_BASE, EPI_PORTK_PINS); /**< inicializa porta K como EPI */

    EPIDividerSet(EPI0_BASE, 1); /**< configura base de clock de EPI */

    EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM); /**< configura EPI como SDRAM */

    EPIConfigSDRAMSet(EPI0_BASE, ( EPI_SDRAM_CORE_FREQ_50_100 |
    EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT), 468); /**< configura clock */

    EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_256MB | EPI_ADDR_RAM_BASE_6); /**< configura tamanho máximo da sdram */

    while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ){_nop();} /**< aguarda status de configuração dos registradores */

    }