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TM4C1290NCZAD: EPI connection with nvSRAM

Eric Ma
Intellectual 2630 points
Part Number: TM4C1290NCZAD


Hi team

My customer have a question about the EPI connection with a 8 bits NV SRAM.

As customer will use UART5 and UART7, so the EPI0S0~S7 would be used as UART function.

Can you suggest how to connect EPI0S8~EPI0S25 to connect with NVSRAM   A0~A15, D0~D7， and how to setup the configuration.

Eric

  • 0
    Guru 26105 points

    Hi,

    I would suggest a better solution - a SPI SRAM, higher speed, possible battery backup, etc, like this one:

    Also there are similar SPI NVSRAM.

  • 0 in reply to Petrei
    Guru 117855 points

    Hi Petrei,

    While "Liking" your unique SPI SRAM "find" - have you (actually) "run the numbers" (calculated) - which then "prove" that this "SPI (serial) device" proves "faster" than an EPI-based, parallel SRAM?

    I'm NOT asking that you "make that calculation" - yet if you "have" those numeric comparisons - that would be most interesting.

    Thanks for sharing your find - good to see you around...    (and thanks for, "rising to my aid" when attacked by, "Do my Homework" crue...)

  • 0 in reply to cb1_mobile
    Guru 26105 points

    Yes, I was thinking about - it is slower than EPI, but, could be better from hardware point of view - the o/p does not specifies why EPI/UART problems, could be an imposed price of end product - the EPI interface for that micro has alternate pins configuration for EPI0..3 and a single pin option for EPI4..7, so he can either change to a micro wih more pins, or look for another solution.

    Depending on application, the SPI option could be a good option - keep the data in some structures and moved/saved/read to/ from "outside" only when needed - actual SRAM is big enough (256KB) - some twenty years ago we had the PC with 256KB RAM running at least Windows 3.1 - but of coarse, the end user knows better his needs.

    Kind regards

  • 0 in reply to Petrei
    Guru 117855 points
    Thank you, Petrei - your response & analysis much appreciated. For an SPI memory device (even a modern "quad") to "out-speed" a parallel memory bus - seemed unexpected... (recall that unless the "address" is simply "bumped" - that SPI usage demands multiple byte transfer - to pass (both) the address & data!)

    When our firm faces such design challenge (as poster presents) is it not best to FIRST accommodate the EPI - and only then the (far lesser) MCU resource "hogs?"

    Poster may also note that - in absence of that "planning" - it is not (that hard) to "bit-bang - UART behavior" - from any 2 GPIO pins!