EK-TM4C1294XL: ADC0 locks up from channel input spike when GPIO external trigger

BP101 said:

After removing an intermediate dongle PCB 3" jumper wires

While your narratives are always delightful - might your presentation of a schematic - serve to, "speed, ease, enhance" the efforts of your "help crue?"     Somehow - i'm unable to "fully grasp" the details of components, inter-connections, & measured values - contained w/in "intermediate dongle PCB."     

We believe the "oft repeated" mention of (long) "dead/buried" MCU serves little purpose.      No one here (caused) its demise - (we're thus guilt-free)  - nor can (most) here be expected to "search for, dig out - and then probe, "Why - that past device (appeared) to work!"     And - as your (auxilliary circuits) have "changed so much during the years" - any attempt at (real) "MCU A vs. MCU B" comparative behavior would prove suspect - would it not?

Schematic added to help explain post and past versions of LM3S ADC having issues with TM4C1294 VREFP voltage limit.

3v3 TVS diode should stop EMF spikes going over VREFP?

/cfs-file/__key/communityserver-discussions-components-files/908/Transient-suppresor-TVS-16kv-ESD9C3.3S_2D00_D.pdf

cb1_mobile said:

How FAST is your D1 (TVS diode)?

Data sheet few posts up +3v3 VRWM, 1ns, +5v BVD yet still PWM spikes sometimes hit 5v scope probe X11 pins.  Had Schottky cathode tied to +3v3 anode at X11 pins, other TI HV inverters do similar for EMF but didn't see any difference other than less signal jitter results. 

cb1_mobile said:

If your resistive divider chain is made with non-smt resistors - on a bread board - might you have created an, "Antenna?"

SMT 1/10th watt chips on bottom of inverter ground plane around these EMF circuits.  Just proved this week dv/dt ringing spikes can be snubbed by slowing down high side FETS. Takes about 420ns gate drive turn on rise time with 100-200ns minimum pulse width for wheel diodes to work effectively. Worked great at 24vdc but at 80v the gate rising edge gets sharp again, under 120ns dv/dt spikes returned.

cb1_mobile said:

Your voltage divider causes signal "EMF" to be (greatly) reduced - presenting just (6.8/1428.8 * EMF {~.005 EMF}) to

All that reduced is the primary PWM signal roughly 500mv down from 1.2v but the spikes still shoot up past VREFP 3v3 and go 1v below ground, average dv/dt is 2.6v constant ringing.

cb1_mobile said:

 You may also add (some) noise immunity by employing small diameter, "shielded cable" - to carry your inverter's EMF signals

Yet the clunky rainbow cable into resistor/capacitor dongle circuits worked all the way up to 160v but even worse spikes were noticed on phase C. Figured 1 more 474k then another 474k added but not much change in the spike peaks.

cb1_mobile said:

Note also that such high resistance (V_Div) is (almost) certain to delay & skew the arrival of the "EMF signal" at your MCU...

These are separated EMF signals twisted pair 6" jumpers, ground wrapped where rainbow cable had parallel ground next to each EMF signal all in same bundled.

That's what I get for trying to reduce footprint. The worst offender high side C, A is quite as church mouse, B seems to feed on high side C left overs. 

Feel your pain - your (higher) voltage BLDC motor causes issues not (often) seen in our firm's 48VDC (and under) BLDC motor world.

I'd have thought that a quality Schottky diode would be faster responding than a TVS diode - note that you added the TVS spec after my return writing.   I'll make the time to review that TVS spec later tonight.

Does it not seem strange that your phase EMF measurements differ - as much as they do?    Might that fact - on its own - enable you to "tease out" valuable data?    I believe that the issue may be influenced by your "custom, BP created, BLDC motor."    To test that theory - cannot you change the phase wiring between Controller Output and Motor - and then either, "match that change" by "re-wiring between the Gate Driver outputs and FET inputs (involves (some) time/effort) OR you may implement that, "Gate Driver to FET change" via modifying the BLDC software.    (may take longer mentally - but no physical effort (wiring) required.)

It will prove beneficial to learn if your "issue" - post this change, "sees the "worst offender" MOVE w/the Motor's re-wiring."     (meaning - the Phase wire - leading to what had been Motor Phase C (at the motor) now becomes "worst offender."    That shifts "offender status" to (almostly certainly) that motor's phase.  

The remaining alternative points to a weakness w/in "FET pair C" - or the signal quality input to that FET pair.   If - after rewiring between Controller FET outputs and your motor - the "worst offender" continues at Controller's Phase C (despite the fact that Phase C now drives a different motor phase) - Phase C (FETs or gate drivers) should, "prepare to make bail."

Again - this process is (another) illustration of the (banned here) KISS method.    We've tried to gain understanding by making the minimal changes - which are expected to glean insight.

Have you considered isolating the ground connections between "Logic Side" and the "Power Side."    Such SiC designs (shown recently @ APEC, Orlando) employ this often - now may be an opportune time for this (excellent noise reducing technique) to rise in your consideration...

I didn't want to over-complicate my response, earlier.    (Ha!)    Might you describe - with (some) detail - what you mean when you describe the ADC as, "locked up?"     Are you absolutely certain that this does not occur (still) if you remove the HV "offending" signals - and employ a cb1-style, "BLDC signal simulator" which is incapable of generating those (unwanted) transient signals.    (i.e. such BLDC motor simulator generates (appropriate) yet "faked" hall signals (either @ 60 or 120°) and produces "MCU friendly" (w/in MCU input spec) varying analog BEMF signals - while monitoring your 3 PWM Phase outputs - and adjusting the hall signal frequency (and F_BEMF) in proportion to your PWM Duty Cycle.)    Most here would be more "accepting" of your "spike diagnosis" - if you could demonstrate LONG PERIODS of successful ADC operation - when "No such spikes" are admitted.     We know you to (sometimes) resist such "test/verification" - yet the value afforded is great - as is your NEED for "real data."

Motors - and the noise they create - so often, "Slow, Complicate, and Confound" BLDC & Brushed Motor, Control Development!     Is it not to your advantage to consider some form of BLDC simulator - incapable of such (dreaded) transients?     And - one last torment - how do you know that the, "Rest of your program runs completely & to specification" and that ONLY the ADC suffers this, "lock-up?"    it is possible - via simple character Lcd - or multiple Leds - to observe your program's regular progression.     Such (also) provides needed insight - appears each/every one of our boards...

Note too:  "lock-up" comes perilously close to the always delightful, "Does not work!"    Surely you've monitored the pertinent ADC Registers - both prior to - and then subsequent - to this (undefined) lock-up...   Sharing of those Register values - pre/post "lock-up" proves of interest & high value...

cb1_mobile said:

Have you considered isolating the ground connections between "Logic Side" and the "Power Side."

Tried last night to source one side of EMF ground only from inverter or from TM4C made no difference or very little. Linear dc supply 24v has isolated winding from 80v source, should help in this case. The difference now is dongle still exists but on side of inverter and decouples only INA240 into ADC0 via single wire. In past dongle decoupled EMF from 3" differential pairs in rainbow ribbon cable topside of inverter PCB. Seems this Guru was doing something right after all and others this forum past clamored rainbow was a source of EMF. The other difference was rainbow differential pairs sourced signal grounds top side PCB from small via ground planes under/near HVIC that run parallel with HO signal into FET. The key was EMF had single 3" wires from dongle into X11 connector pins, decoupling was done on the dongle. A custom PCB can not duplicate decoupling method exactly as it was on the dongle. Ideal method is to place decoupling cap next to MCU analog channel input, perhaps necessary though hard to test that method as we see in this post.

cb1_mobile said:

The remaining alternative points to a weakness w/in "FET pair C" - or the signal quality input to that FET pair.

Those are now source from inverter under side pins via to topside HVIC with 100 ohm series resistors at Hin/Lin and very clean signals captured from 6" runs into X11 header. Phase C is part of Delta winding where feedback to phase A is hard wired. TI seems to design for best case WYE stator bound to face similar unexpected issues, Delta phase has better control of torque speed than WYE ever can. Piccolo team instead jump to 300/600v IGBT, very high DC levels and very costly in my view and typically run from an AC source supply.

cb1_mobile said:

The remaining alternative points to a weakness w/in "FET pair C" - or the signal quality input to that FET pair.   If - after rewiring between Controller FET outputs and your motor - the "worst offender" continues at Controller's Phase C (despite the fact that Phase C now drives a different motor phase) - Phase C (FETs or gate drivers) should, "prepare to make bail."

There is 600ns of propagation delay Hin to HO but seems unrelated with to fast gate drive rise time almost impossible to stop EMF during duty cycle acceleration even at 24v. We can snub it at steady speed reduce EMF but not get it entirely gone using FET body diode alone. Double up low ESR capacitors helps reduce EMF but costly HV and consume far to much PCB space. One idea came from Fairchild forum suggest to add high speed HV diode across DS of high side FET.

cb1_mobile said:

   Might you describe - with (some) detail - what you mean when you describe the ADC as, "locked up?"  

ADC1 still shows MCU temperature changes but ADC0 stops reporting bus voltage/current and zero EMF speed indications occur. Same thing occurs with at 40khz PWM the EMF crashes ADC0 inputs, system with decoupling EMF dongle was good up to 25khz. Oddly bus voltage/current kept reporting but EMF speed channels would suddenly lock up at 40khz, no more samples were processed by the application. POR is required to clear the locked up ADC channels.   

You've added much new detail - yet I view "NO" response to my suggestion to, "Alter the connections between your BLDC Motor and the Controller's 3 Phase output stage!"   Then - measure & observe if, "FET Phase "C" proves (still) the offender.    

Again (to attempt to "sell this test method") - is it not of value to determine if the "unique disturbance - you reported upon "Phase C" - is, "Motor OR FET Phase dominated?"    Might this test have fallen victim to, "Hunch, Guess, Sense?"    Such "real & focused" test measurements usually outperform (unexplained) "beliefs!"

The introduction of "more & more data" - coupled with the avoidance of (any) response to a, "reasonable/worthwhile, test methodology" (firm/I have benefited from that method) - seems not the best means to "encourage" such time/effort investment - in your behalf...    If you deny (any) benefit from my suggested test - it would be preferable to state such - rather than, "completely avoid/bypass."

cb1_mobile said:

You've added much new detail - yet I view "NO" response to my suggestion to, "Alter the connections between your BLDC Motor and the Controller's 3 Phase output stage!"   Then - measure & observe if, "FET Phase "C" proves (still) the offender.    

Point is decoupling very same exact EMF spikes via dongle placed C1/R4 arrested any faulting of ADC0 during acceleration. Of course any negative value input to ADC0 pulls the entire VREFP rail -1v below ground and that needs to be addressed as the offender not the spikes above VREFP. That said being spikes have gone high as +5.7v and never cause ADC0 to lock up.

Changed inverter EMF pickups above ground plane only one end of signal cable grounded either inverter or EK, the EMF spikes top 3.2v maximum. The benefit is higher rotor velocity can be reached prior to crashing ADC0 but the negative portion jotting below ground is the killer. One benefit of lower EMF noise is motor runs quieter so spike below ground must me eliminated via isolated analog coupling medium. Changed C4 to 1nf and EMF was to distorted my surprise it would not even start but C4 of 0.1uf does. Note 4 single ended analog inputs are being pulled -1.0v below ground is not supported and must be corrected at all cost.

cb1_mobile said:

the "unique disturbance - you reported upon "Phase C" - is, "Motor OR FET Phase dominated?"  

Inductive kickback CCEMF is not unique to any single BLDC though held at bay (via circuitry) from entering ADC channel inputs as detailed in TIDA-00778 eliminates all EMF from entry into ADC0 for good reason.

Yet another (past, successful) experiment - "UNTRIED by you" - yet rejected!     You reported "special offense emanating from Phase C" - and now, "Run fast/far" from your own finding.

Some may note that as, "Crazy Making" would they not?    I cede your success to others...    (and predict the arrival of yet (another) self-award)

BP101 said:

dongle circuits worked all the way up to 160v but even worse spikes were noticed on phase C.

Quote from post:  16:27 - 14 April 2017.

Best that you, "identify in advance" - those facts & inputs which you present - and then downplay/discard...   Not for me!

One idea to move all EMF above GND might use a small transformer or perhaps an isolator chip. Either way the TM4C129 ADC is not so forgiving of analog signals in single ended channel mode jotting below VDDA. The EK-TM4C1294XL tied VDDA to VDD and ADC0/1 internal voltage reference or VREFP is set to source VDDA but not VREFA+ shown in schematic.

I believe launch pads HW configuration is causing some ADC0 vulnerability to ambient EMF. Since VREFA+ TP13 has an open ended trace leading out to X11 header allows ambient EMF to enter the MCU via the VREFA+ input.

What say vendors FE why such issue TM4C129 where LM3S8971 was not being at all prone to similar negative spikes? My view is TM4C is a near matching replacement for NRND Stellaris MCU and should work equally well or better with improved immunity to EMF noise.

cb1_mobile said:

Yet another (past, successful) experiment - "UNTRIED by you" - yet rejected!

My friend all BLDC motor phases produce EMF some worse than others depending on the load being driven and where the torque speed loop is being subjected to stress. Nothing will eliminate FET di/dt forward voltage drop jotting below ground perhaps only cover up dv/dt ringing recovery as stated by slowing high side FET or adding VDS capacitance, both are expensive and bad ideas!

You seem to inappropriately focus on the inverter where the ADC being highly sensitive to outside EMF is the primary issue of post.

Indeed - bow to your superior knowledge, experience, cunning.

Can "inappropriate focus" be claimed - at all - via DIRECT RESPONSE to your report of, "Even worse spikes upon Phase C."     Have you now - (unable to make your system work) - somehow risen to (sole) judge/jury - as to what "qualifies" as appropriate?     Really?

(Vendor agents will quickly "line up" - sure to "appropriately focus!"      Yet to do such - must they (now) - ignore your presented findings?)

cb1_mobile said:

Vendor agents will quickly "line up" - sure to "appropriately focus!"

Then vendor agents would be barking up the wrong tree since all phases (ABC) produce EMF not just phase C.

cb1_mobile said:

  Have you now - risen to (sole) judge/jury - as to what "qualifies" as appropriate?

In this case focus on method of single ended channel lockup by signals not being tolerated by TM4C ADC0. All ADC0 monitored signals jot below ground, datasheet showing single input minimum not to exceed VDDA seems to indicate LMI was sharing bad circuitry or LM3S8971 was more tolerant how far below ground a single ended channel could go. I lean more to the second part after witnessing same EMF present in the motor RDK but never locked the ADC channels.

Lets take a look at TM4C1294 how ADC0 VREFP defaults to an internal undocumented voltage source versus VREFP using external VREFA+ with decoupling capacitors C3,C4 ! Perhaps ADC0 is more tolerant of EMF jotting below ground in the external reference mode? All the sample filter equations are way off value, hence a reluctance to try the external reference but have considered cutting TP13 open trace leading out to X11 header pin. Configuring channels differential should eliminate ADC0 lock up but EK has AGND tied to GND so it can't be taken negative by an external reference. Otherwise what is the difference other than getting better precision in a single ended sample? 

BP101 said:

cb1_mobile

Vendor agents will quickly "line up" - sure to "appropriately focus!"

Then vendor agents would be barking up the wrong tree since all phases (ABC) produce EMF not just phase C.

cb1_mobile said:

Is it not fair - and (most) appropriate then - to ask why you emphasized,  "Worst case coming from Phase C?"   (You must have had some reason!) Presenting such data - and then "running from it" - does little to inspire confidence - is that not true?

The real question you should be asking why EMF is perhaps effecting VREFP (post focus) and why TM4C1294 datasheet shows ADC0 single ended mode VadcIN = (VinP-VinN_ (note: e,f) (0v/VDDA) with an internal reference. With external reference VadcIN = -(VrefA+ - VrefA-) (note: d,f) does this infer analog signal below VDDA=(0v) are then tolerated by the TM4C1294 ADC0? 

Note (d) states see figure 27-28 page 1866 does little to elaborate nonsense equation, e.g. is that a dash inferring to value or subtract VrefA- from VrefA+ ? How does this note relate to the EK-TM4C1294XL where AGND is tied to GND? What steps must be take to improve the launch pad EMF noise immunity so the community can actually prototype test circuits from the X11 header ADC0 with negative EMF swings? 

Then ask why the LM3S8971 datasheet shows only a minimum of -300mv for all inputs yet no ADC specific limits of VadcIN relative to the VREF?   

Yesterday tested external precision reference (TL431) R41 removed and the REFA+ current at +2v5 with 10R series is well over 575ua. Check schematic edited R41, TP13 location.

TM4C1294NCPDT datasheet states VREFA+ values 330ua MIN, 440ua MAX @3v3 yet it loads down the TL431 open reading of +3v2. An LDO 3v3 feeds the TL431 cathode (IKA) limited by 1kR to 3ma so plenty of current is available to regulate. Find it odd that external VREFA+ drags down the TL431 if it only sources 440ua but will again adjust the Ref pin voltage 1.25v max with 10ma IKA and cathode is well below LAB tested value of 10ma since 3ma is the input limit set by 1kR.

BP101 said:

To confuse the matter

True that!

Does the "ever expanding" scope of your posts - in (any) way - properly enable vendor agents to recognize (which) "protest du jour" - they are to attend?

BP101 said:

analog signals typically are bipolar in character and not simply unipolar.

I'm surprised to learn that there exists a "typical" analog signal - and that it tends to "bipolar."    Might you "support" such a conclusion?     Your "opinion" - minus attribution - proves (again) unconvincing.  

In opposition - do not (many), "op-amps, analog comparators, DACs, & analog others" now exist - which happily & effectively - operate from a Single, unipolar supply?"   (which proves "inhospitable" to "true" bipolar signals)  

Indeed there exist similar, "bi-polar" analog devices - but to describe either as "typical" - is an extreme "reach" (and an incorrect one) - even for you...

As your frustration grows - your desire to "bend the world to your defense" - may provide (neither) the shortest - nor strongest - path to success!

cb1_mobile said:

I'm surprised to learn that there exists a "typical" analog signal - and that it tends to "bipolar."

That is the unique difference between digital and analog voltages and just because TM4C1294 ADC can samples only above 0v don't classify it a true analog device in my opinion, even in differential mode. A good ADC requires split supply and samples down to nearly full negative rail especially unique to digital audio reproduction that desires the full PP analog wave sampled.  

Good example is the INA240 single ended supply differential amplifier fails miserably to capture the negative current half cycle in equal symmetry to the positive half cycle. There is real and unreal and the real thing Coke yet Spock would say nothing unreal exists.

This B.P. post deserves "entombment" in bronze.

May I suggest that the "unique difference" between "digital & analog voltages" is NOT Polarity (as you most recently claim) - but instead - the ability of the analog voltage to assume (essentially) unlimited, continuous voltage levels.    In contrast - digital voltages usually assume one of two - well separated (i.e. Discontinuous) - voltage levels.    Most all (proper) Engineering Texts support this viewpoint.    (Mr. Mims III's "hobby paperback" was unlikely to support your, "Bipolar as the unique (Analog vs. Digital) difference" claim.)

As further disproof of that (latest/entombed) claim - you must have noted that "long standard, RS-232 level voltages" (which are clearly Digital) happily  "SWING between 2 Bipolar Voltage Levels!"   (RS-232 spec lists ±12-15V (thus bi-polar) - wrt ground.)    Thus tonight's, (Gospel according to B.P.) "Digital voltages "must" be unipolar" - has been clearly demonstrated to be untrue!

One doubts that "Coke or Spock" (alone or in combination) can "make real" your claims:

• "Analog voltages are "typically" Bipolar"    (There is NO such "typical!")
• (if we can parse your writing)  "Digital voltages are (always) Unipolar."    (Except when they are not!)

True bipolar analog audio signals existed a century prior to acclaimed ADC  SAR acting more linear in behavior, 0v up to supply rail. To say that an analog signal has only a DC polarity is just wrong, if anything a linear SAR ADC mimics a true analog bipolar ADC device that requires split supply to convert bipolar analog signal into digital numbers.

My opinion remains the word analog is being used inappropriately to express the SAR ADC digital conversion and should be reclassified as a linear device capable of capturing variable signals above ground only.

cb1_mobile said:

As further disproof of that (latest/entombed) claim - you must have noted that "long standard, RS-232 level voltages" (which are clearly Digital) happily  "SWING between 2 Bipolar Voltage Levels!"

Again not without some kind of modification can a binary digital signal produce RS232 digital attributes. How is that an a signal with no AC sine wave aspect, having no bipolar attributes is ever called analog remains mind boggling. RS232 is more of an extended digital reproduction and in no way is it analog. The science community is far behind in correcting 20th century wave form classification definitions. Just because you/I agree with this current electronic oddness don't in my opinion make it an absolute in the 21st century.

Please try to answer Table 27-45 why input equation of single ended with external VREFA+ ; what is meant by VREFA- Min , VREFA+ Max ?? Does the VREFA- infer the channel signal input can then extend below ground without effecting the ADC internal SAR conversion process? If you look at the table you will see the single ended input with internal reference sourced from VDDA shows 0v Min, VDDA Max

BP101 said:

To say that an analog signal has only a DC polarity is just wrong

And - might you identify - by whom & where - was such statement made?    An analog signal may enjoy unipolar or bipolar voltage levels - again - there is NO/ZERO "typical" analog signal.

BP101 said:

RS232 is more of an extended digital reproduction and in no way is it analog.

No one here (unless twas you) made any claim that "RS232 signals are analog!"    RS-232 line drivers indeed produce, "Bipolar, Digital Signals" - effectively refuting your claim that Digital Signals (must) always be unipolar.

Your presentation of your (many) "opinions" is fine - but should be so noted - and not represented as "fact."     (which too often - they are NOT!)

cb1_mobile said:

RS-232 line drivers indeed produce, "Bipolar, Digital Signals" - effectively refuting your claim that Digital Signals (must) always be unipolar.

Actually RS232 is not really even digital though perhaps more analog like and rather a bipolar serial data stream reproduction representing a unipolar digital signal.

cb1_mobile said:

An analog signal may enjoy unipolar or bipolar voltage levels - again - there is NO/ZERO "typical" analog signal.

Yet in context of SAR ADC ignores variable signals below ground, again in my opinion makes it a linear variable single capture conversion to digital and not at all analog. The word analog infers an AC single not so much DC unless mechanical gauges are in play but the science community likes to blur reality it seems. Who knew the Higgs' Boson particle actually exits or gravity waves exist in space other than Spock!

cb1_mobile said:

Your presentation of your (many) "opinions" is fine - but should be so noted - and not represented as "fact."     (which too often - they are NOT!)

Who ever claimed my ideas beliefs have or were ever accepted by the science community (rhetorical).  It takes thinking outside the box often lost in endowment grants, money for nothing chicks for free ideology. 

Still no answers for the ADC VREFA+ question?  BTW your Hall testing method is in our SW as an FOC simulator using the same ADC0 has been running for 10 days IOT without interruption. Like to mention AN6076 equation (27) adds Qgs1 when it actually factors out in (28) subtracting VgsTh (5v), gate drive @ Fairchild / Onsemi (Non- Isolated DC-DC converters) forum.  

Re: Still no answers...
You are aware of firm/my dislike for 4C129 family - choosing far faster & far more capable ARM M4s - w/superior TFT capability (size & speed).

So - I'd have to start from square 1 in answer to your VREFA+ question - and we have (only) LX4F boards (hundreds) and 4C123 ones.

Should vendor fail to arrive - and you remain stuck - I'll see if a boardless, "2nd opinion" may help...

Bob - great to note your arrival - & well explained.    Yet - do note - I got "moderated" (earlier) for suggesting "DRM suppression"  was, "inconsistent & unclear."   (which proves - absolutely - the case!)

Ho Bob,

Bob Crosby said:

No, there are ESD protection diodes on the input signal that will forward bias causing currents in the substrate that will affect the ADC conversion if ADC input is less than ground regardless of which reference is used.

That seemingly would infer the ADC channel ESD clamps perhaps might allow EMF kickback below ground to enter the channel inputs. Oddly the LM3S8971 datasheet suggested any voltage below ground on a channel pin would be ignored in the conversion process. Perhaps an external bidirectional TVS would help in that case as the unidirectional 3v3 TVS seemed to do nothing for spikes near 5.7v. Again for some reason the jot below ground was not locking up ADC0 when channel bypass caps were mounted on PCB with parallel ground signal pairs 3" away from the EMF source and single 3" wire to channel input X11 header. So moving the bypass further from the MCU pin to the inverter even with twisted pair into X11 header fails to reduce the EMF chatter. One would think adding 100pf bypass caps on the X11 ADC channel input pins might help but did not help. 

Question: Are the ESD protection diodes shown in figure 27-17 bidirectional or unidirectional?

Bob Crosby said:

If your point is that we did not make that clear by specifying a valid range for VREFA-, I agree.

Agree It seems there is more to the story, will add info to forum post concerning VREFA+ input pin restrictions.

Good for you - congrats...

BP101 said:

adding Schottky diodes cathode +3v3 anode to EMF signals

Such (use of Schottky diode) "was" my earlier (far earlier) suggestion.     Would not your writing be more clear if you noted the diode's anode tied to the ADC input pin?   (indeed the EMF signals "enter there" but there exists NO "EMF input" on any (known) MCU!)     Might your success enable some "splashing of the green" - especially for he who first made Schottky diode suggestion?

cb1_mobile said:

Such (use of Schottky diode) "was" my earlier (far earlier) suggestion.  

Yet as I stated last post adding a diode causes very bad signal behavior and should not be added into the circuit. The idea put forth in datasheet is ADC channel input = 0v MIN, not -1.5v with diode added. Perhaps if C1 could somehow be 0.047uf it might stop the signal push down below ground but 1nf/1000pf distorted the required EMF to much for SW to decode zero crossing events. Oddly a channel TSHn=0x4/Nsh16 was found to cause issues with these lower level EMF conversions. A sample (EMF) hold value TSHn-0x2/Nsh8 or Fconv=1600Ksps Rs=500 ohms reduced overall EMF spike amplitudes to my great surprise.

Same principal goes for adding caps at input of gate drive, a very bad idea being a path for dv/dt at ground flowing into the gate drive inputs. Spent hours adding 100pf caps then removing all of them after seeing parasitic EMF or dv/dt on HVIC Hin/Lin inputs.

A timer now triggers ADC0 when any PWM pin drives output which might actually be better since current signal is both +/- and exceeds any 80/50us period of active phase on time. 

BP101 said:

adding a diode causes very bad signal behavior and should not be added into the circuit. The idea put forth in datasheet is ADC channel input = 0v MIN, not -1.5v with diode added.

My friend - you set (both) "land & sea" records for unique operational difficulties - never "seen" - nor to be replicated by we "mortals."

I suggested - the quite standard implementation of a Schottky Diode - Anode tied to the MCU's ADC input pin(s) - Cathode tied to "stiff" 3V3.    (this diode clamps the + input voltage to just above 3V3)

Are you reporting - that the addition of that Schottky Diode - exactly as described (just above - in highlight) causes that ADC pin to register -1V5?   Really?

We must note that you provide "no operating conditions" under which that (unusual - to be kind) measurement was claimed to occur.    How did you make such measurement - and under which operating conditions?

From where does the diode obtain or link to a, "Negative Voltage Source" - to impose the -1V5 - as you claim?     And while you claim "very bad signal behavior" - what constitutes that "bad behavior?"    And just how do you charge the Schottky Diode as the SOLE cause agent?

cb1_mobile said:

Are you reporting - that the addition of that Schottky Diode - exactly as described (just above - in highlight) causes that ADC pin to register -1V5?   Really?

No - As reported a Schottky diode was tested prior to this post and again tried per TIDIA-00778 schematic. A diode cathode tied to +3v3 pushes pulse peaks below positive rail and forces the original signal magnitude excessively below ground. The original signal PP magnitude jotting above VREFP has to go somewhere and it does but in a bad way shoots far under (0v) ground.

TVS diode (3v3) shown in posted schematic is working far better than realized and clamps EMF spikes (@1ns) analog channel signal under 4v. The other nice aspect is 12.8pf very low capacitance of OnSemi TVS diode. The TVS clammed signal may jot -500mv below ground at times but the EK-TMS4C1294XL appears unaffected as ADC/MCU temperature remains constant. 

cb1_mobile said:

I would expect (instead) that a low capacitance (fast) Schottky diode would allow an input signal to (slightly) exceed the 3V3 rail (perhaps by 200-300mV)!    

Don't disagree with signal (ceiling) rather the signal (floor) single pulse jots far push below ground, highly excessive at -1.5v. 

cb1_mobile said:

Your scope's "Ground connection lead" MUST be removed - replaced instead w/a strategically located/placed "scope probe sized," ground connected "loop" - for any such measurements to be "trustworthy."

Perhaps so perhaps difficult X11 header signal input always to find ground nearby for probe collar ground spring to contact. In this case 2 analog EMF channel inputs exist next to free ground pins on X11 header.

cb1_mobile said:

your high number of board failures (as you've reported)

If two launch pads are a high number, "Mable slam the door on that exaggerating sales man."

Not sure what you are inferring as 2 boards seem to have issues not from EMF abuse rather some kind of intra layer PCB resistance near VDDA from VIA holes exist. One is a brand new launch pad and never connected X11 header pins to any EMF source. They both POR and seem to function normally even with low 250 ohm resistance JP31 removed VDDA.

BP101 said:

Don't disagree with signal (ceiling) rather the signal (floor) single pulse jots far push below ground, highly excessive at -1.5v. 

Thus you have (now) removed your (earlier) claim that the Schottky diode "clamps the input signal BELOW" the voltage level imposed upon the diode's cathode.   Good that!

Yet mon ami - should you & I visit Las Vegas - and bet (everything) upon your "-1V5" measurement (still unsupported via (repeatedly requested) scope caps) we'd (almost certainly) be "Washing Dishes" until "rescue funds" arrive...   (which just may - enable (some/slight) "green" to return to your (otherwise) beyond barren back yard (aka: B.P.'s Blown FET burial ground) populated by (many) 2-headed amphibians & reptiles...    BTW - how "goes" ticket sales?     (staff/I can only "hold off" OSHA for so long...)

cb1_mobile said:

Thus you have (now) removed your (earlier) claim that the Schottky diode "clamps the input signal BELOW" the voltage level imposed upon the diode's cathode.   Good that!

Was speaking in general terms pros/cons of adding Schottky relative to circuit R/C implications upon the ADC channel datasheet specifications. Testing EMF with probe ground spring X11 header pins started with a bang. Oddly +160v DC power supply boot up a 0.1uf/200v bypass ceramic blew on inverter, even with a 1 second soft start and 330R/10watt in series it shorted (bang!!). Seems the poly 0.22uf/600v (inverter) was doing little to stop these EMF spikes and 0.1uf had been leaking friendly EMF into the ADC0-SS0, perhaps for some time. Deserve this for repurposing some parts from one PCB to another.

Arrive at that EMF conclusion after installing a new 0.1uf/200v ceramic the application would not detect the same threshold zero crossings previously worked great, high voltage supply. Perhaps EMF is still to high even with three 474kR in series. Will now test a single 2.2M ohm after Saturday replacing one of the three 474k with 100k the signal (single pulse) floor returned back to -1.5v and ceiling was 4.7v-5v at high voltage. At 24v supply the signal ceiling tops near 1.6v and floor -200mv to -250mv. 

Thought of using an opto coupler though a 3ms delay would not be good in this EMF application but are commonly used in FB circuits of power supply.   

Feel your pain - and surely your "backyard graveyard" will enjoy the variation in its diet. (ceramic cap now "lies" among the twisted/discolored FETs)

There exist newer - and faster - opto couplers.

Before I "go broke" at the gaming tables - I'd bet (heavily) that proper ISOLATION between your Motor Supply and MCU Supply (SEPARATE GROUNDS!) would do WONDERS in reducing the transient horrors - you regularly/repeatedly must face.     You may search/find/review EVAL Boards for SiC Power FETs (shown recently (last month) @ APEC, Orlando) - which "ALL" employ such "isolation" to escape similar issues...    

Check this vendor first - yet "ADI" has several "isolator" ICs which can be expected to substantially "quiet" your board(s)!

cb1_mobile said:

Before I "go broke" at the gaming tables - I'd bet (heavily) that proper ISOLATION between your Motor Supply and MCU Supply (SEPARATE GROUNDS!)

Seems to me grounds are isolated by having complete separate transformer windings. Perhaps the HVIC inverter ground plane being connected to the DC switcher ground plane could be more isolated by placing several zero ohm resistor chips between them. The bad ceramic cap HVB+ (0.1uf/200v) bypassed on bottom ground plane was causing most undesired EMF spike issues. Also added a 0.1uf/250v Mylar top side FET B+ rail to top side edge ground plane arrested larger 4v-5v spikes. Perhaps the 0.22uf/600v did/does little to stop spikes for PWM frequency below 20kHz.

Have discovered TVS diodes now with much reduced series resistance puts out spike fires.  The signal peaks appear like fire flames in the TVS clamp signature being very similar to OnSemi lab testing of positive ESD captures. Far better was placing a fast 3ns/100ma silicon diode (EMF signal) cathode to ground versus cathode 3v3. Now the EMF signal spikes keep below 3v3, mostly hang near 2.5v upon reaching steady state rotor velocity.

Capture shows EMF for CH1/CH2 where width of spike snubbing varies horizontally by adding/subtracting width periods.

BP101 said:

grounds are isolated by having complete separate transformer windings.

What is the treatment of the VSS (Ground) pin on each of your Gate Driver ICs?      

Those gate-driver signal inputs must respond to your MCU's drive signal (referenced to MCU Ground) - yet the gate-driver outputs must reference (either) the "floating" High-Side FET (common) or the Low-Side's "FET Ground."    

Have you tried - with power completely OFF (and - as always - at your full & sole risk) to "ohm out" MCU ground vs. gate driver ground vs. FET (Low Side) ground?     Should those (all) be tied together - you are NOT isolated!

BP101 said:

the HVIC inverter ground plane being connected to the DC switcher ground plane could be more isolated by placing several zero ohm resistor chips between them.

You did NOT really mean this - did you?    (or you are not awake)    Do not those 0Ω resistors MARRY the Motor Supply Ground to MCU Ground?     How can that be called "Isolated?"     (what would "preferred tech source" (Mims III) say about this?)

cb1_mobile said:

 Do not those 0Ω resistors MARRY the Motor Supply Ground to MCU Ground?     How can that be called "Isolated?"    

Disagree with the idea HV/LV grounds can be safely and totally separated even with an LA battery source.

cb1_mobile said:

Should those (all) be tied together - you are NOT isolated!

My thought is the linear supply LV/HV grounds must be common at some PCB location or current can not flow between the two and HVIC/FET gates will not switch properly if grounds are totally separated.

cb1_mobile said:

Do not those 0Ω resistors MARRY the Motor Supply Ground to MCU Ground?

We can not totally separate the two linear supplies return current paths the MCU must also share, would that not be disastrous? Ideally from the FET perspective it must see ground the world around or in other words have current returns to both HV/LV supply rails.

Again the LV/HV linear grounds become common at the inverter ground plane, typical motor drive PCB.  The +24 linear LV buck down switcher provides +5v/+15v and has separate ground/+5v small #24 jumper (wires) to the launch pad X11 header for feeding the 3v3 LDO regulator.  The +15v has a single wire lead into the HVIC supply rail on the inverter ground plane side.

cb1_mobile said:

You may search/find/review EVAL Boards for SiC Power FETs (shown recently (last month) @ APEC, Orlando) - which "ALL" employ such "isolation" to escape similar issues...

it is assumed that your "opinions" did not benefit from your review of the - (proper) & expert) - isolation techniques - noted above.      (which conflict wildly w/your views)

cb1_mobile said:

it is assumed that your "opinions" did not benefit from your review of the - (proper) & expert) - isolation techniques - noted above

I don't think a non-isolated gate driver can function in the way you are suggesting, can it?

Checking TIDA-00778 uses three UCC27714 non-isolated IGBT gate drivers and has tied together on development PCB (LV/HV) AGND to GND via solid copper.

Remain skeptic how can LV source isolated ground ADC accurately measure a HV source without a return ground path being shared by the MCU, is that even possible? 

BP101 said:

I don't think a non-isolated gate driver can function in the way you are suggesting, can it?

No one here (other than you) ever suggested such, "Non-Isolated Gate Driver!"     

I'm unwilling to "Do the work for you" - especially when you fail to display properly focused, productive effort - even after such direction is supplied in your behalf.

To appease this vendor - you may wish to read/review this ISOLATED GATE DRIVER'S SPEC: "UCC21520."      Indeed there are other (similar) Isolator devices - I chose SiC FET Isolation boards for you earlier -as they better match your higher voltage BLDC Motor requirements.    There's no evidence you've made any effort to search/find/review...   (those SiC FET boards - I suspect - "more down your alley!")

To ease your effort - and those of (interested) others:

9.2 Typical Application

The circuit in Figure 34 shows a reference design with UCC21520 driving a typical half-bridge configuration which could be used in several popular power converter topologies such as synchronous buck, synchronous boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.

You may (clearly) note that the "MCU Side's" Ground (Left Side) is Separate & Independent from the, "Gate-Driver/FET Side's" Ground.    (Right Side)  

This Isolation greatly reduces "Ground Noise,Bounce,"Chatter" (all highly suspect as contributing to your (many) design woes)!         Such "Ground defects" happen when the device starts switching - operating current consumption increases suddenly - and the PWM "EDGES" (NOT the PWM Frequency) generate (very) high frequency transients.

 Yet you (claimed) such Isolated grounds "could not work!"    Your past post w/that claim was "frozen in time" (for your acknowledgement, consideration & review).

For FIVE YEARS (perhaps even longer) you have been trying to develop a BLDC Controller - and yet (most always) challenge the suggestions of others!      (who (perhaps) have greater awareness/experience/tech savvy)