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TM4C1231E6PM: UART0 communication problem

Part Number: TM4C1231E6PM

Hello Everyone,

I am using UART-0 of tm4c1231e6pm. While I starts transmitting data (about 1024 bytes) via uart, in between I get "Receive_Timeout_Interrupt()" from uart even if no data is being transmitted from outside to uart.

I noticed that the data bytes received are the one that i transmitted to uart. Is there any special recommend settings (Hardwrae/Software wise) for using UART-0?

  • URVI,
    First, if you don't plan to use UART for receiving, then maybe you should not enable the Tx timeout interrupt.
    Next, there are two possible reasons for what you are receiving on U0RX:
    Either you have you hardware configured for internal loopback (the signals sent to U0TX are replicated into the RX line) - there is a TivaWare function that controls this setting, called UARTLoopbackEnable();
    Or you have hardware interference outside the MCU IC.
    Bruno
  • Hi URVI,
    I'd like to add comments on top of Bruno's. The received timeout means that the receive FIFO is not empty and no further data is received before the timer timeouts. What this means is that you have some data sitting in the FIFO which are not read by the CPU until the timer timeouts. Even though you are not transmitting anything but nevertheless the unread data sitting in the receive FIFO triggers the receive timeout interrupt. Think of the mechanism as serving a reminder to the CPU that there are still unread data. As suggested by Bruno, you will need to enable the receive timeout interrupt in order to generate a timeout interrupt. If you are receiving the same data as transmitted then you most likely have an internal loopback enabled. Please also check your board routing, do you have the TX and RX pins loopbacked together.
  • Charles Tsai said:
    Think of the mechanism as serving a reminder to the CPU that there are still unread data.

    Charles, I don't really see the receive timeout (RT) interrupt as such.

    The issue addressed by the RT is to avoid missing/ignoring the last few bytes of a reception, when the RX trigger is set for a number of bytes greater than what just arrived.

    With a more numeric explanation: you could have your RX set to trigger at 50% of the FIFO buffer, hence it will annoy the program execution only when 8 bytes come in. If the last piece of the message contains only 3 bytes, the RX would not trigger until 5 more bytes were received later (if ever). Hence, if the UART engine stays "some time" without receiving anything AFTER the last byte, it triggers RT, and the ISR can still service whatever is there. "Some time" is explained in one of the documents, but is obviously a bit more than the amount of clocks that it would take for a new byte to come in on the configured uart speed.

  • Hi Bruno,
    I agree with you. Perhaps I wasn't clear with my writing. It would have been better if I had phrased it as 'Think of the mechanism as serving a reminder to the CPU that there are still unread data less than the programmed FIFO threshold that have expired the timer .'
  • Now that's a long sentence!
    No worries - I just wanted to share the experience... Truth is I had not understood the reason for RT interrupts for some time into "my carreer", only figured it out when I started dealing with more complex UART buffers and DMA. Before that, it had been just the standard copy/paste of RX/RT parameters because they seemed to work!
  • Charles Tsai said:
    I agree with you.

    Oh my - does the forum scoreboard now reveal: "Blind Squirrels 2 - Experts 0?"     (of course this reporter (also) - well qualifies - as a squirrel - and blind!)

    Often the best "defense/response" is the simple, "You are right!"     Bravo for that recognition - Charles!

    We note that (some) here - so often will - "twist/turn/distort" - anything to (resist) the (contrary - yet often correct) viewpoint of others...

  • When someone is right, I don't find it hard to agree with him. :-)
  • That's a great quality - reflects good character...