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TMS570LC4357: Flash and RAM uncorrectable ECC errors identification

Gael Le Moing
Expert 1020 points
Part Number: TMS570LC4357


Hi,

I am gathering information about ECC logic programmed inside the Cortex-R5F CPU, and as far as I understand, Level 2 Flash and RAM inside the TMS570LC are viewed by the core through the same AXI master interface, where ECC uncorrectable errors are signalled to the Error SIgnalling Module (ESM) through ESM 2.3 "Cortex-R5F Core - Bus ECC".

As it goes through an ESM group 2 error, I have the ESM High priority interrupt that is triggered and I can install a routine to manage the system when the error occurs.

But I need to have a specific behaviour in case the error has been detected on the RAM, and an other behaviour if the error has been detected on the flash.

How could I get this information from the core? Or from anywhere inside the TMS570 (RAM, Flash, Interconnect, ...)?

Thanks!

Gael

  • 0
    TI__Guru 59540 points
    Hello Gael,

    There are separate ESM error flags for RAM and Flash ECC errors. The ESM channels are defined in the ESM Channel Assignment table within the device specific datasheet.
  • 0 in reply to Chuck Davenport
    Expert 1020 points
    Hello Chuck,

    As I understand from the Datasheet ESM channel assignments table (Table 6-45), all L2FMC ECC related errors are not double bit ECC errors on data read (that are detected by the core).
    Those flagged by the Cortex-R5F are flagged to the ESM through the Core Bus ECC fatal error, i.e. group 2 channel 3 of the ESM.
    Am I right on this?
    Thanks
    Gael
  • 0 in reply to Gael Le Moing
    TI__Guru 59540 points
    Hello Gael,

    My apologies for my original answer which doesn't account for the architectural differences in the TMS570LC43x compared with our earlier Hercules devices. In this specific device, the RAM and Flash reside on the L2 Bus which causes some latency when they are accessed and, therefore, latency in reporting of the uncorrectable error conditions. Because of this latency, we rely on the event bus mechanism within the R5F to flag the uncorrectable error and rout this through the EPC. The draw back of this is we loose the context of the uncorrectable error regarding whether it was in Flash or RAM and the ability to latch the address for which it occurred. In short, we cannot discern if an uncorrectable error originates in SRAM or Flash.
  • 0 in reply to Chuck Davenport
    Expert 1020 points

    Thanks, this answers my question.

    Best regards,

    Gael