Hi,
In the Cortex-R5F documentation, I see that the ARM or Thumb state on exception entry depends on the TEINIT primary intput of the Cortex.
I'd like to know if the exception entry is done in ARM state or Thumb state in the TMS570LC4357, but I can't find this information in the TMS documentation.
Does anyone has this information and where it is documented?
Best regards,
Gael