Hello,
I noticed in the technical report for this microprocessor, they were able to achieve performance level d. I am curious why it was only able to achieve PL d.
The functional safety of my application will need to meet performance level e. Could I achieve this by having more redundancy in the design, such as having two RM46L852 processors in my design? Or is PL e not obtainable with the TI MCUs? This seems like it would be overkill as it would have 4 total CPUs checking for inputs as well as 4 sensors.
Thanks,
Christian Gabor