TMS570LC4357: Are there any known issues running a TMS570 (4357) / RM57 with an external input clock of 20 MHz in terms of PLL lock?

Hello Jarsh,

The PLL related erratum that you are referring to is independent of the PLL input frequency as long as the input crystal frequency is compliant with the datasheet specification. More details about the PLL issue and the prescribed work around are listed in the errata documentation available on the device product page located here TMS570LC4357. There are slightly different versions of the PLL errata in each of the silicon revisions.

If you have any difficulty locating the information, please let me know.