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RM48L952: HALCOGEN is generating invalid code for DCC2 when N2HET2_0 is selected as clock source 1

Thiago Esteves
Prodigy 85 points
Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN,

I was willing to use N2HET2_0 as clock source 1 of the DCC2 to verify my PWM. I was checking why it wasn't working and I realized that the generated code by HALCOGEN (04.06.01) is not corrected. See the code below:

VCLK as clock source 1 :

dccREG2->CNT1CLKSRC = (uint32)((uint32)10U << 12U) | /** DCC Enable Key */
                                                     (uint32) DCC2_CNT1_VCLK; /** DCC2 Clock Source 1 */

N2HET2_0 as clock source 1:

dccREG2->CNT1CLKSRC = (uint32)((uint32)10U << 12U) | /** DCC Enable Key */
                                                     (uint32) DCC2_CNT1_N2HET2_0; /** DCC2 Clock Source 1 */

As you can see, the define is changed correctly, but the DCC enable key is generated for both which is incorrect by the RM48L952 device description Table 6-18. DCC2 Counter 1 Clock Sources (page 74). I changed the value manually to remove the DCC enable key for N2HET2_0 and now everything is working.

Kind Regards,

Thiago Esteves

  • 0
    TI__Guru 59540 points
    Hello Thiago,

    Yes, I agree that there seems to be a disconnect between the code implementation and the cited table. I also see that there is a discrepancy between the table interpretation of the enable key function and what is described in the TRM register description for DCCCNT1CLKSRC which indicates that the enable key is used to enable the clock source selection. I also agree based on your results that the table is correct and that the register description and implemented code should be updated. Thank you for chasing this down!! I will forward this information to both our documentation and Halcogen teams.
  • 0 in reply to Chuck Davenport
    TI__Genius 14205 points

    Hi

    Bug Ticket SDOCM00122923 raised to fix this issue. The fix will be rolled out in upcoming HALCoGen release Jul'17.