TMS570LC4357: EMIF clock for asynchronous access

Hello Gael,

Answers below.

Gael Le Moing said:

• Is it 150MHz as indicated in chapter "6.6.2 Clock domains" of the TMS570LC4357 datasheet (see table 5-2. Clock Domain Timing Specification")?
• Is it 100MHz due to the "tc(CLK)" minimum value of 10ns found in "Table 6-38. EMIF Synchronous Memory Switching Characteristics"? >> Then, is this constraint on tc(CLK) only applicable for synchronous accesses?

These assumptions are correct. For asynchronous accesses, the limit is 150MHz and for synchronous accesses 100MHz is the limit.

Gael Le Moing said:

From a FPGA designer in our team, it looks like the it would be interesting to use the EMIF clock signal (if available), even for asynchronous accesses:

• Do you confirm that the EMIF_CLK signal is output at any time, regardless of the EMIF configuration?
• Does this pin can output a signal of 150MHz if VCLK3 can be configured at 150MHz?

This should be true. The EMIF_CLK signal output is not gated by EMIF access and should be available all the time.