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tm4c129xnczad power on failure



Hi,

I've a strange behaviour regarding our production board based on TIVAC129xnczad chipset.

We observed on some board that the VDDC pin generate the reference 1,2V for few seconds and then fall down to ground: this issue cause a stuck of microcontroller.

Following the reference design, we mounted a C153 capacitor of 4,7uF but then we changed with 3,3uF as the maximum value was indicated as 4uf. Below our part code:

C152: KEMET  C0603C104K5RACTU

C153: KEMET T521D475M063ATE075

C153: KEMET T494D335K050AT

This issue can be observed after a burn out of the board at about 50 celsius on climatinc room.

We know also that on document "ErrataTIVA.pdf" there are two workaround: SYSCTL#09 and SYSCTL#16 and they are referred to silicon revision 1 and 2, but we have rev3 instead.

 

Do you have any idea on why the micro is not generating the VDDC reference or generate it for a while? Could be the oscillator cause this issue?

Regards,

Marco Crivellari

 

  • Marco,
    There are no schematics on your post, "C153" doesn't help us to help... Maybe you did try? There are a couple of blank squares within the post...
    Do you use a crystal on your board, or is it the internal oscillator?
    Can you verify if any code even runs? Can you program the board, or does the MCU die right away?
    I've had similar problems when I was not starting up VDDA properly, but that's a blank shot with lack of further info.
    Bruno
  • Marco Crivellari said:
    We observed on some board that the VDDC pin generate the reference 1,2V for few seconds and then fall down to ground

    While not explicit - that statement suggests that (some) of your custom boards do NOT share this problem - is that true?     (i.e. do some work?)

    It would be helpful if you'd indicate the rough percentage of boards failing.     You may wish to check the "failed pile" for any commonalities - especially if they differ from the boards which work.    (if any)

    Should (some) boards work - you have the "most helpful" opportunity to perform, "A-B Testing & Comparison."     You may wish to scope the key power waveforms - save them - and then compare.    (working vs. non-working boards.)

    You may then wish to (temporarily sacrifice) one working board - by removing the VDDC components - and then using those to replace the related components upon a non-working board.     Should the "non-working" board then perform - you've identified a component issue.     As you note - VDDC components have strict requirements - several of your components may be mismarked - or simply mistaken.

    We have noted that both 3V3 supply and the input to VDDA must be strong/solid - to avoid such VDDC issues.    It is always wise to "scope monitor" both of those voltages - especially during, "Power Up."

    And "Reset" must be properly treated (and monitored at power-up) - it too proves suspect...

  • From your post I'm left with several questions

    Is C153 on the VCC line? If so, how is it routed and do you have lower capacity, higher frequency caps in parallel?

    What's the rise time of your 3V3 supply? Have you checked the TI datasheet to see if there are minimum rise specifications and that you meet them?

    What are you using for your reset circuit? Generally reset must remain asserted until the core power supply has a chance to stabilize. One check you could make on a set of failed boards is to wire the reset low and see if the core supply comes up. If it does that's an indication that you need a faster rising 3V3 supply or a supervisory IC with a longer reset time, perhaps both.

    Robert
  • May we note what appears to be conflicting statements w/in your post?

    Your Subject line notes a, "Power On" failure.   (we cannot (easily) "quote" from the subject line)

    Marco Crivellari said:
    on some board that the VDDC pin generate the reference 1,2V for few seconds and then fall down to ground

    And this quote (appears) to confirm such failure (via, "w/in a few seconds") but (only) if we can link that "few seconds" to, "After Power On."

    And further down w/in your post:

    Marco Crivellari said:
    issue can be observed after a burn out of the board at about 50 celsius

    Now the board has been heated w/in a chamber - has it been unpowered - while rising from ambient to 50°C?     Is it (only) under these (heated to 50°C) conditions that your board experiences, "Power On failures?"     None of this has been explained - nor detailed...

    Devil so often in the details - and these 3 sets of facts are presented independently - and it is unclear, "How or even If" they are linked...      Request your clarification - thanks...

  • Marco, take a look at this document:
    www.ti.com/.../spmu365c.pdf
    Specifically on page 6/6 of the schematics - there are several caps, there are VDDA pins on the MCU... There is a detailed view of the power switcher... There are lots of information regarding the MCU power circuit.
    Your partial image probably won't help people to help you...
    Bruno
  • Hi,
    first of all I'm sorry but I missed the schematics in the previous post, I tried but I was not able to do that.

    Now that schematics is attached I can reply to your questions:
    - C152 and C153 are connected to VDDC with a small path and provide lower capacity, higher frequency caps in parallel
    - I'm using an oscillator FXO-HC73 SERIES (see schematics attached)

    In order to reply cb1_mobile questions, I try to explain better my situation.

    All our boards are production boards, they are assembled and tested by our supplier.
    When we receive boards, we pick up them and put into our climate chamber in order to simulate the normal function of our instruments
    (typically the internal temperature is about 50 celsius).
    The board are put into the chamber at power off, and then power on. After 48 hours we take back the board from the chamber and check them.

    At this step we power on again the board and use a serial interface that show us the booting and application sequence. One of the
    following condition can appear:
    1. power on correctly , normal function
    2. doesn't power on at all (no VDDC)
    3. the board generate the VDDC for two/three seconds, show boot sequence and partial application and then stuck

    This is why I used a subject "power on failure". I'm sorry if it was not clear at first, now I hope it is.

    BR

    Marco Crivellari

  • Thank you - that's (some) help - yet several questions & requests have (not) been honored.

    1) What percentage of your boards are failing? That's important - and (still) unknown.

    2) Is it correct to believe that your board is "Powered & Operating continuously" while "in the chamber" and at temperature for 48 hours? Are you monitoring & communicating w/the board - while it is w/in the chamber? (there exist special thermal ports which enable both power & signals to "pass thru" the chamber.) You never describe your attempt (and the results) of operating your board while "in the chamber."

    3) You remove the boards (from the chamber) - and then "Power again." But unstated is the board temperature - upon removal. And how much time passes - between board removal - and your (new) Power On test. Most chambers which we employ allow for "temperature cycling" and it is this "cycling" - along w/controlled "shock/vibration" which (really) builds confidence in the board's correctness & robustness! If you're (only) testing occurs upon "the removal of the board from the chamber" - that appears (very much) "non-standard!"

    4) It was suggested that you "exchange the VDDC components" from one or several "working boards" with those removed from "failing boards." This provides insight to MCU vs. component error - and is (known) to be of good diagnostic value...

    Do understand that the strategy for repairing 1% failure is much different than that during 20% failure! (this is why this "percentage of failures" was requested - (earlier) - and again now...

  • I think my earlier questions on reset and 3V3 supply still stand. As well
    - What happens to the 3V3 supply during core failure?
    - Do you have more capacitance on your 3V3 power inputs than shown? If not you are very undercapped. Bruno gave you a reference to the TI evaluation board but it is low on capacitors as well. I'd want at least one high frequency cap on each VDD pin plus larger caps. I think TI has some recommendations (just looked it up Application report AN01283 would be a start, there may be something newer).
    - Finally, the way you've drawn and named your core power supply makes me wonder if you are using it for other purposes.

    Robert
  • Robert Adsett said:
    the way you've drawn and named your core power supply makes me wonder if you are using it for other purposes.

    That's quite a valuable "get" - thanks Robert.

    Such "savings" - by "sharing" the MCU key power supply - deserve "great care/consideration" and are NOT classically recommended!

  • Such a use of core supplies is usually forbidden IME.

    Robert
  • Hi.

    The 3V3 signal is ok during core failure, and we have followed all design rules about 3V3 regarding capacitors.

    The percentage of failure is about 10%, and yes we use special ports for power on and monitoring. The boards are cycled to room temperature before power off and typically they are checked (power on) after about 15 min.

    An important news: we found the root cause of power fail.
    The VDDA in our design is separated from VDD and use an electrolytic capacitor 1uF. This capacitor loose isolation during thermal cycles and drain down an abnormal current that cause VDDA to drop down.

    Thanks you all for your suggestions.


    BR
    Marco Crivellari
  • Good for you - glad that you "found" the "weak link."     You must now consider whether you wish to change "ALL SUCH VDDA CAPS!"    (in time/heat/stress - those "passing" may degrade.)

    Do note that your "solution" was (earlier) identified for you.    (presented 13 May '17 @ 10:24 ...  quoted below)     The award of "Verify Answer" should follow.   (to that 13 May post)

    cb1_mobile said:
    We have noted that both 3V3 supply and the input to VDDA must be strong/solid - to avoid such VDDC issues.

  • Marco,
    Good that you found the issue!
    cb1, shan't I beg for a green first? The only blind shot I took - 3 hours before your post - was exactly regarding VDDA!
    (Note that such experience came from YOUR guidance a few years ago, might I confess!)
    Bruno
  • cb1_mobile said:
    Good for you - glad that you "found" the "weak link."     You must now consider whether you wish to change "ALL SUCH VDDA CAPS!"    (in time/heat/stress - those "passing" may degrade.)

    More than that I think. I think there should be a stress test of the board. Marco has found a weak link in the design, this could be either component or board related. If component then switching to a different capacitor (not a new capacitor of the same part number) may solve the thermal issue, but it would need to be tested.

    Marco, you earlier stated that 50 was the typical temperature. You should test beyond that to find weak points. Ideally you want to do something like a HALT test. At the least I'd elevate the temperature significantly above typical. If possible I'd cycle well below freezing as well and as fast as you could.

    Robert

  • Robert Adsett said:
    If possible I'd cycle well below freezing as well and as fast as you could

    What??? Why? Just to find more defective boards?

    No, my friend - just ship your products as they are, and pray that users don't stress them too much!  :)

  • Silly me, why would you want to find design problems before shipping?

    Robert
  • Robert Adsett said:
    Silly me, why would you want to find design problems before shipping?

    Indeed - and that's (almost) as silly as Bruno's "begging" for a Green...     B's, "Not starting up VDDA properly" is NOT the same as "Lack of strong/stiff power @ VDDA!"      Starting up VDDA was not the issue - maintaning it (past those few opening seconds) was!

    Words HAVE meaning - thus the virtue of attending schools beyond engineering.     Nevertheless - I'd click Green (in your behalf) - if I could...

  • Oh, life... That's the kind of comment one gets for discussing engineering with lawyers...
    :)
    All good fun - still I will not begin submit my posts to a board of advisers before hitting enter!
    Repeated might it be: I'm a business man before being an engineer, and a mechanical engineer before being a electron inquirer!
    And if all that fails, I can always blame on English not being my native tongue...
  • Glad you acknowledged, "good fun." (and the value of (careful) wording...)

    We note that "Electronic, Mechanical, & electron inquirer" - (all) escape, "native tongue!" BTW - you do great job in your writing - (maybe, somewhat) resulting from your time here - and the care & planning you put forth are (sure) to improve your outcomes...

    That "care/planning" - when practiced more widely - would greatly reduce the rushed, "How to ..." - which leads inevitably to, "Does NOT Work!"
  • Thank you for the kind words...
    That "native language" escape is a flaw one, I'm long past the line where such could honestly be used...
    Always hoping the learning curve on this forum will allow me to publish some Tiva-for-dummies-and-engineers-alike pages sometime in the future - for no profitable reason at all, but rather, as a tool for personal/company learning and improvement.
    Regards
    Bruno

  • Bruno Saraiva said:
    for no profitable reason at all

    Yet for (some) here - past under the "power" of smart & enhanced blondes - profit IS a most necessary goal...

    And...is it not (somewhere) written - that one GETS (deserves) what one PAYS FOR?